Abstract
In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.
Original language | English |
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Pages (from-to) | 281-284 |
Number of pages | 4 |
Journal | Journal of Electronic Packaging, Transactions of the ASME |
Volume | 128 |
Issue number | 3 |
DOIs | |
Publication status | Published - 2006 Sept |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Mechanics of Materials
- Computer Science Applications
- Electrical and Electronic Engineering