Transient thermal analysis for board-level chip-scale packages subjected to coupled power and thermal cycling test conditions

Tong Hong Wang, Chang Chi Lee, Yl Shao Lai, Yu Cheng Lin

Research output: Contribution to journalReview article

14 Citations (Scopus)

Abstract

In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.

Original languageEnglish
Pages (from-to)281-284
Number of pages4
JournalJournal of Electronic Packaging, Transactions of the ASME
Volume128
Issue number3
DOIs
Publication statusPublished - 2006 Sep 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Mechanics of Materials
  • Computer Science Applications
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Transient thermal analysis for board-level chip-scale packages subjected to coupled power and thermal cycling test conditions'. Together they form a unique fingerprint.

  • Cite this