Transition-code based linearity test method for pipelined ADCs with digital error correction

Jin Fu Lin, Soon Jyh Chang, Te Chieh Kung, Hsin Wen Ting, Chih Hao Huang

Research output: Contribution to journalArticlepeer-review

22 Citations (Scopus)


A transition-code based method is proposed to reduce the linearity testing time of pipelined analog-to-digital converters (ADCs). By employing specific architecture-dependent rules, only a few specific transition codes need to be measured to accomplish the accurate linearity test of a pipelined ADC. In addition, a simple digital Design-for-Test (DfT) circuit is proposed to help correctly detect transition codes corresponding to each pipelined stage. With the help of the DfT circuit, the proposed method can be applied for pipelined ADCs with digital error correction (DEC). Experimental results of a practical chip show that the proposed method can achieve high test accuracy for a 12-bit 1.5-bit/stage pipelined ADC with different nonlinearities by measuring only 9.3% of the total measured samples of the conventional histogram based method.

Original languageEnglish
Article number5648403
Pages (from-to)2158-2169
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number12
Publication statusPublished - 2011 Dec

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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