Two-dimensional inverse discrete cosine transform processor

Jar-Ferr Yang (Inventor)

Research output: Patent

Abstract

A two-dimensional inverse discrete cosine transform (2-D IDCT) processor comprises cosine angle index generators, pipelined multipliers and a symmetrical kernel. The 2-D IDCT processor of the invention has a five-stage pipelined structure for carrying out a coefficient-by-coefficient 2-D IDCT algorithm and can be operated at a clock rate of more than 50 MHz to achieve a pixel rate of about 400 MHz.
Original languageEnglish
Patent number5636152
Publication statusPublished - 1800

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@misc{037c815c4eb74e67bdbf702c90a4febd,
title = "Two-dimensional inverse discrete cosine transform processor",
abstract = "A two-dimensional inverse discrete cosine transform (2-D IDCT) processor comprises cosine angle index generators, pipelined multipliers and a symmetrical kernel. The 2-D IDCT processor of the invention has a five-stage pipelined structure for carrying out a coefficient-by-coefficient 2-D IDCT algorithm and can be operated at a clock rate of more than 50 MHz to achieve a pixel rate of about 400 MHz.",
author = "Jar-Ferr Yang",
year = "1800",
language = "English",
type = "Patent",
note = "5636152",

}

TY - PAT

T1 - Two-dimensional inverse discrete cosine transform processor

AU - Yang, Jar-Ferr

PY - 1800

Y1 - 1800

N2 - A two-dimensional inverse discrete cosine transform (2-D IDCT) processor comprises cosine angle index generators, pipelined multipliers and a symmetrical kernel. The 2-D IDCT processor of the invention has a five-stage pipelined structure for carrying out a coefficient-by-coefficient 2-D IDCT algorithm and can be operated at a clock rate of more than 50 MHz to achieve a pixel rate of about 400 MHz.

AB - A two-dimensional inverse discrete cosine transform (2-D IDCT) processor comprises cosine angle index generators, pipelined multipliers and a symmetrical kernel. The 2-D IDCT processor of the invention has a five-stage pipelined structure for carrying out a coefficient-by-coefficient 2-D IDCT algorithm and can be operated at a clock rate of more than 50 MHz to achieve a pixel rate of about 400 MHz.

M3 - Patent

M1 - 5636152

ER -