In this paper we present two accurate and efficient modeling techniques for CMOS circuits to enhance the performance of test generation and fault simulation for bridging faults. The first one is a fault modeling technique for inter-gate bridging faults. The second one is an accurate threshold determination method. The accuracy of our model achieved because all the following factors, including device parameters, voltage operation range of each logic value, resistance of ON-transistors, resistance of bridging faults, and test patterns are considered. The efficiency is achieved due to the simplicity of the solution methods that require no complex circuit level simulation. Experimental data show that SPICE like accuracy can be efficiently.
|Number of pages||6|
|Journal||Proceedings of the Asian Test Symposium|
|Publication status||Published - 1996 Dec 1|
|Event||Proceedings of the 1996 5th Asian Test Symposium, ATS'96 - Hsinchu, Taiwan|
Duration: 1996 Nov 20 → 1996 Nov 22
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering