Two-stage hot-carrier-induced degradation of p-type LDMOS transistors

Jone F. Chen; Tzu Hsiang Chen; Deng Ren Ai

doi:10.1049/el.2014.2901

Two-stage hot-carrier-induced degradation of p-type LDMOS transistors

Jone F. Chen, Tzu Hsiang Chen, Deng Ren Ai

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (I_Dlin) shift (I_Dlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (N_IT) leads to an initial increase in I_Dlin shift. On the other hand, two competing mechanisms, i.e. increase in N_IT generation and increase in electron trapping, are responsible for the saturated I_Dlin shift when the stress time is longer.

Original language	English
Pages (from-to)	1751-1753
Number of pages	3
Journal	Electronics Letters
Volume	50
Issue number	23
DOIs	https://doi.org/10.1049/el.2014.2901
Publication status	Published - 2014 Nov 6

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1049/el.2014.2901

Cite this

@article{9224a5102d214970bd9ae97ab661395b,

title = "Two-stage hot-carrier-induced degradation of p-type LDMOS transistors",

abstract = "Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.",

author = "Chen, {Jone F.} and Chen, {Tzu Hsiang} and Ai, {Deng Ren}",

note = "Publisher Copyright: {\textcopyright} The Institution of Engineering and Technology 2014.",

year = "2014",

month = nov,

day = "6",

doi = "10.1049/el.2014.2901",

language = "English",

volume = "50",

pages = "1751--1753",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "John Wiley & Sons Inc.",

number = "23",

}

TY - JOUR

T1 - Two-stage hot-carrier-induced degradation of p-type LDMOS transistors

AU - Chen, Jone F.

AU - Chen, Tzu Hsiang

AU - Ai, Deng Ren

N1 - Publisher Copyright: © The Institution of Engineering and Technology 2014.

PY - 2014/11/6

Y1 - 2014/11/6

N2 - Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.

AB - Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.

UR - http://www.scopus.com/inward/record.url?scp=84912061600&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84912061600&partnerID=8YFLogxK

U2 - 10.1049/el.2014.2901

DO - 10.1049/el.2014.2901

M3 - Article

AN - SCOPUS:84912061600

SN - 0013-5194

VL - 50

SP - 1751

EP - 1753

JO - Electronics Letters

JF - Electronics Letters

IS - 23

ER -

Two-stage hot-carrier-induced degradation of p-type LDMOS transistors

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this