Abstract
Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.
| Original language | English |
|---|---|
| Pages (from-to) | 1751-1753 |
| Number of pages | 3 |
| Journal | Electronics Letters |
| Volume | 50 |
| Issue number | 23 |
| DOIs | |
| Publication status | Published - 2014 Nov 6 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Two-stage hot-carrier-induced degradation of p-type LDMOS transistors. / Chen, Jone-Fang; Chen, Tzu Hsiang; Ai, Deng Ren.
In: Electronics Letters, Vol. 50, No. 23, 06.11.2014, p. 1751-1753.Research output: Contribution to journal › Article
TY - JOUR
T1 - Two-stage hot-carrier-induced degradation of p-type LDMOS transistors
AU - Chen, Jone-Fang
AU - Chen, Tzu Hsiang
AU - Ai, Deng Ren
PY - 2014/11/6
Y1 - 2014/11/6
N2 - Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.
AB - Hot-carrier-induced device degradation of high-voltage p-type lateral diffused metal-oxide semiconductor (LDMOS) transistors is investigated. A two-stage linear region drain current (IDlin) shift (IDlin shift increases rapidly at the beginning of stress but tends to saturate when the stress time is longer) is observed. Technology computer-aided-design simulations and direct current current-voltage measurement results suggest that the decrease of residual fabrication interface traps (NIT) leads to an initial increase in IDlin shift. On the other hand, two competing mechanisms, i.e. increase in NIT generation and increase in electron trapping, are responsible for the saturated IDlin shift when the stress time is longer.
UR - http://www.scopus.com/inward/record.url?scp=84912061600&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84912061600&partnerID=8YFLogxK
U2 - 10.1049/el.2014.2901
DO - 10.1049/el.2014.2901
M3 - Article
AN - SCOPUS:84912061600
VL - 50
SP - 1751
EP - 1753
JO - Electronics Letters
JF - Electronics Letters
SN - 0013-5194
IS - 23
ER -