Ultra-low-power, high-density spintronic programmable logic (SPL)

Kang L. Wang, Hochul Lee, Farbod Ebrahimi, Pedram Khalili Amiri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A non-volatile spintronic programmable logic (SPL), based on a 3-teriminal magnetic tunnel junction (MTJ), is presented and simulated using a compact device model. The SPL structure is compatible with CMOS technology and can be fabricated in the back end of line (BEOL). The proposed SPL exploits the gate-voltage-modulated spin Hall effect (V-SHE) switching, which combines the voltage controlled magnetic anisotropy (VCMA) effect and SHE, as a parallel configuration method. The VCMA modulates the coercivity of the MTJ, reducing the critical current for the SHE to change the state of MTJs. This allows the SPL to achieve 100x faster configuration speed due to the parallel configuration, and 32% area reduction because of minimized transistors in the write circuit, compared to conventional spin transfer torque memory (STT-RAM) based programmable logic.

Original languageEnglish
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages169-172
Number of pages4
ISBN (Electronic)9781479953400
DOIs
Publication statusPublished - 2016 Jul 29
Event2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
Duration: 2016 May 222016 May 25

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2016-July
ISSN (Print)0271-4310

Other

Other2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
CountryCanada
CityMontreal
Period16-05-2216-05-25

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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