TY - GEN
T1 - Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme
AU - Huang, Chi Ray
AU - Wu, Kuan Lin
AU - Wu, Chung Han
AU - Chiou, Lih Yih
N1 - Funding Information:
The authors would like to thank the Ministry of Science and Technology of Taiwan for grants supports (MOST 106-2221-E-006-239 and MOST 105-2218-E-006-024) and National Chip Implementation Center for their support through facilities for design, fabrication, and measurement.
Publisher Copyright:
© 2018 IEEE.
Copyright:
Copyright 2019 Elsevier B.V., All rights reserved.
PY - 2018/4/26
Y1 - 2018/4/26
N2 - Leakage power dissipation has become a major problem in advanced process technologies, especially in large SRAM designs. The use of adaptive techniques is a promising approach to decreasing power consumption through dynamic scaling of the supply voltage of integrated circuits. To obtain maximum reduction in leakage power, an adaptive data retention voltage (DRV)-regulating scheme is proposed to achieve substantial saving of SRAM standby power. The proposed design supports DRV operation from the above-threshold to subthreshold regions and self-adapts to process, voltage, and temperature variations by using the proposed DRV monitor. According to the measurement results, the proposed design using 90 nm CMOS technology exhibits maximum leakage savings of 71.5%.
AB - Leakage power dissipation has become a major problem in advanced process technologies, especially in large SRAM designs. The use of adaptive techniques is a promising approach to decreasing power consumption through dynamic scaling of the supply voltage of integrated circuits. To obtain maximum reduction in leakage power, an adaptive data retention voltage (DRV)-regulating scheme is proposed to achieve substantial saving of SRAM standby power. The proposed design supports DRV operation from the above-threshold to subthreshold regions and self-adapts to process, voltage, and temperature variations by using the proposed DRV monitor. According to the measurement results, the proposed design using 90 nm CMOS technology exhibits maximum leakage savings of 71.5%.
UR - http://www.scopus.com/inward/record.url?scp=85057072477&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS.2018.8350944
DO - 10.1109/ISCAS.2018.8350944
M3 - Conference contribution
AN - SCOPUS:85057072477
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Y2 - 27 May 2018 through 30 May 2018
ER -