Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme

Chi Ray Huang, Kuan Lin Wu, Chung Han Wu, Lih Yih Chiou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Leakage power dissipation has become a major problem in advanced process technologies, especially in large SRAM designs. The use of adaptive techniques is a promising approach to decreasing power consumption through dynamic scaling of the supply voltage of integrated circuits. To obtain maximum reduction in leakage power, an adaptive data retention voltage (DRV)-regulating scheme is proposed to achieve substantial saving of SRAM standby power. The proposed design supports DRV operation from the above-threshold to subthreshold regions and self-adapts to process, voltage, and temperature variations by using the proposed DRV monitor. According to the measurement results, the proposed design using 90 nm CMOS technology exhibits maximum leakage savings of 71.5%.

Original languageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538648810
DOIs
Publication statusPublished - 2018 Apr 26
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
Duration: 2018 May 272018 May 30

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2018-May
ISSN (Print)0271-4310

Other

Other2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
CountryItaly
CityFlorence
Period18-05-2718-05-30

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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