Unambiguous I-cache testing using software-based self-testing methodology

Ching Wen Lin; Chung Ho Chen

doi:10.1109/ISCAS.2014.6865495

Unambiguous I-cache testing using software-based self-testing methodology

Ching Wen Lin, Chung Ho Chen

Institute of Computer and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We propose an unambiguous instruction cache software-based self-testing methodology that can generate a reliable result to precisely determine the test passed or not. We present testing cases that cause ambiguous cache testing results and propose five principles of test pattern selection to prevent these situations from occurring. To preserve the order of March sequence in testing an I-cache, we leverage cache bank and cache disable operations. In this way, we are able to implement any March algorithm without violating the sequence order. Finally, we present a case study for ARM v5 ISA processor that has an 8KB instruction cache. We use the March C- algorithm and achieve 100% of inter-word coverage and more than 97% of intra-word coverage evaluated by the RAMSES simulator.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1756-1759
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865495
Publication status	Published - 2014 Jan 1
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 2014 Jun 1 → 2014 Jun 5

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country/Territory	Australia
City	Melbourne, VIC
Period	14-06-01 → 14-06-05

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2014.6865495

Cite this

Lin, C. W., & Chen, C. H. (2014). Unambiguous I-cache testing using software-based self-testing methodology. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 1756-1759). Article 6865495 (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865495

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abstract = "We propose an unambiguous instruction cache software-based self-testing methodology that can generate a reliable result to precisely determine the test passed or not. We present testing cases that cause ambiguous cache testing results and propose five principles of test pattern selection to prevent these situations from occurring. To preserve the order of March sequence in testing an I-cache, we leverage cache bank and cache disable operations. In this way, we are able to implement any March algorithm without violating the sequence order. Finally, we present a case study for ARM v5 ISA processor that has an 8KB instruction cache. We use the March C- algorithm and achieve 100% of inter-word coverage and more than 97% of intra-word coverage evaluated by the RAMSES simulator.",

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Lin, CW & Chen, CH 2014, Unambiguous I-cache testing using software-based self-testing methodology. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865495, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 1756-1759, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 14-06-01. https://doi.org/10.1109/ISCAS.2014.6865495

Unambiguous I-cache testing using software-based self-testing methodology. / Lin, Ching Wen; Chen, Chung Ho.
2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 1756-1759 6865495 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - We propose an unambiguous instruction cache software-based self-testing methodology that can generate a reliable result to precisely determine the test passed or not. We present testing cases that cause ambiguous cache testing results and propose five principles of test pattern selection to prevent these situations from occurring. To preserve the order of March sequence in testing an I-cache, we leverage cache bank and cache disable operations. In this way, we are able to implement any March algorithm without violating the sequence order. Finally, we present a case study for ARM v5 ISA processor that has an 8KB instruction cache. We use the March C- algorithm and achieve 100% of inter-word coverage and more than 97% of intra-word coverage evaluated by the RAMSES simulator.

AB - We propose an unambiguous instruction cache software-based self-testing methodology that can generate a reliable result to precisely determine the test passed or not. We present testing cases that cause ambiguous cache testing results and propose five principles of test pattern selection to prevent these situations from occurring. To preserve the order of March sequence in testing an I-cache, we leverage cache bank and cache disable operations. In this way, we are able to implement any March algorithm without violating the sequence order. Finally, we present a case study for ARM v5 ISA processor that has an 8KB instruction cache. We use the March C- algorithm and achieve 100% of inter-word coverage and more than 97% of intra-word coverage evaluated by the RAMSES simulator.

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Unambiguous I-cache testing using software-based self-testing methodology

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