Unified architectural tradeoff methodology

Chung-Ho Chen, Arun K. Somani

Research output: Contribution to journalConference article

4 Citations (Scopus)

Abstract

We present a unified approach to assess the trade-off of architecture techniques that affect mean memory access time. The architectural features we consider include cache hit ratio, processor stalling features, line size, memory cycle time, the external data bus width of a processor, pipelined memory system, and read by-passing write buffers. We demonstrate how each of these features can be traded off to achieve the desired performance. The performance of an architecture feature is quantified in terms of cache hit ratio based on the equivalence of mean memory delay time. This paper investigates the implication of architectural tradeoffs on the pin count, memory system design, and on-chip cache area for microprocessor systems.

Original languageEnglish
Pages (from-to)348-357
Number of pages10
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
Publication statusPublished - 1994 Jan 1
EventProceedings of the 21st Annual International Symposium on Computer Architecture - Chicago, IL, USA
Duration: 1994 Apr 181994 Apr 21

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Data storage equipment
Microprocessor chips
Time delay
Systems analysis

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

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Unified architectural tradeoff methodology. / Chen, Chung-Ho; Somani, Arun K.

In: Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA, 01.01.1994, p. 348-357.

Research output: Contribution to journalConference article

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