Unified VLSI systolic array design for LZ data compression

Shih Arn Hwang; Cheng Wen Wu

doi:10.1109/92.931226

Unified VLSI systolic array design for LZ data compression

Shih Arn Hwang, Cheng Wen Wu

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

Hardware implementation of data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. In this paper, we propose several serial one-dimensional and parallel two-dimensional systolic-arrays for Lempel-Ziv data compression. A VLSI chip implementing our optimal linear array is fabricated and tested. The proposed array architecture is scalable. Also, multiple chips (linear arrays) can be connected in parallel to implement the parallel array structure and provide a proportional speedup.

Original language	English
Pages (from-to)	489-499
Number of pages	11
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	9
Issue number	4
DOIs	https://doi.org/10.1109/92.931226
Publication status	Published - 2001 Aug 1

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/92.931226

Cite this

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author = "Hwang, {Shih Arn} and Wu, {Cheng Wen}",

note = "Funding Information: Manuscript received May 12, 1998; revised April 10, 1999 and February 4, 2000. This work was supported in part by the National Science Council, R.O.C., under Contract NSC89-2218-E007-063. The authors are with the Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan (e-mail: cww@ee.nthu.edu.tw). Publisher Item Identifier S 1063-8210(01)00691-6.",

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Unified VLSI systolic array design for LZ data compression

Abstract

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