TY - JOUR
T1 - V2X
T2 - An automated tool for building SystemC-based simulation environments in designing multicore systems-on-chips
AU - Hung, Shih Hao
AU - Tu, Chia Heng
AU - Liaw, Yuh Hung
N1 - Funding Information:
This research was supported in part by Ministry of Economic Affairs in Taiwan under grant: MOEA 99-EC-17-A-01-S1-034, and in part, by National Science Council in Taiwan under grant: NSC 100-2219-E-002-028.
PY - 2013/1
Y1 - 2013/1
N2 - Simulation methodologies have been widely utilized to aid hardware/software co-design and shorten the development cycles of systems-on-chips (SoCs). For a complex multicore system, traditional hardware description languages (HDLs), such as Verilog and VHDL, consume too much time in a simulation and are far too slow to perform parallel programs and modern operating systems. Instead, SystemC provides a higherlevel environment to reduce the simulation time and is often a better choice for hardware/software co-design. For existing HDL-based chip designs, it is possible to automatically convert them to SystemC or even higher-level functional descriptions to improve the simulation speed and enable hardware/software co-design. However, existing tools failed to accomplish that for a complex multicore SoC, such as the OpenSPARC T1. Therefore, we investigated the problems encountered by two most popular converting tools, Verilator and V2SC, and developed our own tool, called V2X, to overcome the problems. In our case study, V2X successfully translated the 8-core OpenSPARC T1 SoC (approximately 300,000 lines of Verilog code) into SystemC and significantly reduced the simulation time by 40 times for the user. In addition, this article discusses the two-stage translation scheme which makes V2X more powerful than existing tools and the quick replay method for automatic generation of chip verification suites for the new SystemC-based simulation.
AB - Simulation methodologies have been widely utilized to aid hardware/software co-design and shorten the development cycles of systems-on-chips (SoCs). For a complex multicore system, traditional hardware description languages (HDLs), such as Verilog and VHDL, consume too much time in a simulation and are far too slow to perform parallel programs and modern operating systems. Instead, SystemC provides a higherlevel environment to reduce the simulation time and is often a better choice for hardware/software co-design. For existing HDL-based chip designs, it is possible to automatically convert them to SystemC or even higher-level functional descriptions to improve the simulation speed and enable hardware/software co-design. However, existing tools failed to accomplish that for a complex multicore SoC, such as the OpenSPARC T1. Therefore, we investigated the problems encountered by two most popular converting tools, Verilator and V2SC, and developed our own tool, called V2X, to overcome the problems. In our case study, V2X successfully translated the 8-core OpenSPARC T1 SoC (approximately 300,000 lines of Verilog code) into SystemC and significantly reduced the simulation time by 40 times for the user. In addition, this article discusses the two-stage translation scheme which makes V2X more powerful than existing tools and the quick replay method for automatic generation of chip verification suites for the new SystemC-based simulation.
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U2 - 10.1080/02533839.2012.726024
DO - 10.1080/02533839.2012.726024
M3 - Article
AN - SCOPUS:84872283388
SN - 0253-3839
VL - 36
SP - 48
EP - 62
JO - Chung-kuo Kung Ch'eng Hsueh K'an/Journal of the Chinese Institute of Engineers
JF - Chung-kuo Kung Ch'eng Hsueh K'an/Journal of the Chinese Institute of Engineers
IS - 1
ER -