Variability study of silicon nanowire FETs

Yi Bo Liao, Meng-Hsueh Chiang, Keunwoo Kim, Wei-Chou Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this work, impact of device variability for silicon nanowire FETs is assessed and SRAM design implication is presented based on 3-D numerical simulation. Both the conventional and junctionless nanowire FETs are shown to be sensitive to structural variation whereas the former is more tolerable. Both the circular wire and non-circular wire cases for feasible SRAM design with a focus on read noise margin are included in our study.

Original languageEnglish
Title of host publicationTechnical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
Pages46-49
Number of pages4
Publication statusPublished - 2011 Nov 23
EventNanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 - Boston, MA, United States
Duration: 2011 Jun 132011 Jun 16

Publication series

NameTechnical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
Volume2

Other

OtherNanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
CountryUnited States
CityBoston, MA
Period11-06-1311-06-16

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Liao, Y. B., Chiang, M-H., Kim, K., & Hsu, W-C. (2011). Variability study of silicon nanowire FETs. In Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 (pp. 46-49). (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011; Vol. 2).