Variation-aware comparative study of 10-nm GAA versus FinFET 6-T SRAM performance and yield

Peng Zheng; Yi Bo Liao; Nattapol Damrongplasit; Meng Hsueh Chiang; Tsu Jae King Liu

doi:10.1109/TED.2014.2360351

Variation-aware comparative study of 10-nm GAA versus FinFET 6-T SRAM performance and yield

Peng Zheng, Yi Bo Liao, Nattapol Damrongplasit, Meng Hsueh Chiang, Tsu Jae King Liu

Doctoral Degree Program on Nano-Integrated-Circuit Engineering

Research output: Contribution to journal › Article › peer-review

17 Citations (Scopus)

Abstract

This paper benchmarks the performance of gate-all-around (GAA) MOSFETs against that of optimized silicon-on-insulator FinFETs at 10-nm gate length. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for both device structures. The yield of six-transistor SRAM cells implemented with these advanced MOSFET structures is then investigated via a calibrated physically based compact model. The GAA MOSFET technology is projected to provide for 0.1 V lower minimum cell operating voltage with reduced cell area.

Original language	English
Article number	6951350
Pages (from-to)	3949-3954
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	61
Issue number	12
DOIs	https://doi.org/10.1109/TED.2014.2360351
Publication status	Published - 2014 Dec 1

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2014.2360351

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abstract = "This paper benchmarks the performance of gate-all-around (GAA) MOSFETs against that of optimized silicon-on-insulator FinFETs at 10-nm gate length. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for both device structures. The yield of six-transistor SRAM cells implemented with these advanced MOSFET structures is then investigated via a calibrated physically based compact model. The GAA MOSFET technology is projected to provide for 0.1 V lower minimum cell operating voltage with reduced cell area.",

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AU - Chiang, Meng Hsueh

AU - Liu, Tsu Jae King

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AB - This paper benchmarks the performance of gate-all-around (GAA) MOSFETs against that of optimized silicon-on-insulator FinFETs at 10-nm gate length. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for both device structures. The yield of six-transistor SRAM cells implemented with these advanced MOSFET structures is then investigated via a calibrated physically based compact model. The GAA MOSFET technology is projected to provide for 0.1 V lower minimum cell operating voltage with reduced cell area.

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Variation-aware comparative study of 10-nm GAA versus FinFET 6-T SRAM performance and yield

Abstract

All Science Journal Classification (ASJC) codes

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