Vertical MOSFET with a leveling, surrounding gate fabricated on a nanoscale island

X. Zheng, M. Pak, J. Huang, S. Choi, K. L. Wang

Research output: Contribution to conferencePaperpeer-review

11 Citations (Scopus)

Abstract

A novel vertical MOSFET with several new structural features is presented. These features can lead to significant chip area saving and performance improvement. They include a vertical island with nanoscale thickness; superimposed source and drain; a leveling and surrounding gate; a withdrawn S-B junction, which can lead to a near zero junction depth; and a natural connection from the channel to the substrate, which can be taken advantage of for the realization of dynamic threshold and for the elimination of floating-body effect.

Original languageEnglish
Pages70-71
Number of pages2
Publication statusPublished - 1998
EventProceedings of the 1998 56th Annual Device Research Conference - Charlottesville, VA, USA
Duration: 1998 Jun 221998 Jun 24

Other

OtherProceedings of the 1998 56th Annual Device Research Conference
CityCharlottesville, VA, USA
Period98-06-2298-06-24

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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