VLSI architecture and implementation for speech recognizer based on discriminative Bayesian neural network

Jhing Fa Wang, Jia Ching Wag, An Nan Suen, Chung Hsien Wu, Fan Min Li

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

In this paper, we present an efficient VLSI architecture for the stand-alone application of a speech recognition system based on discriminative Bayesian neural network (DBNN). Regarding the recognition phase, the architecture of the Bayesian distance unit (BDU) is constructed first. It association with the BDN we propose a template-serial architecture for the path distance accumulation to perform the recognition procedure. A corresponding architecture is also developed to accelerate the discriminative training procedure. It contains the intelligent look-up table for the sigmoid function. In comparison to the traditional one-cable method, the memory size reduces drastically with only slight loss of accuracy. Combining the proposed hardware accelerators with the cost efficient programmable core, we took the most out of both programmable and application-specific architectures including performance, design complexity, and flexibility.

Original languageEnglish
Pages (from-to)1861-1869
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE85-A
Issue number8
Publication statusPublished - 2002 Aug

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Fingerprint Dive into the research topics of 'VLSI architecture and implementation for speech recognizer based on discriminative Bayesian neural network'. Together they form a unique fingerprint.

Cite this