VLSI architecture designs for effective H.264/AVC variable block-size motion estimation

An Chao Tsai, Kuan I. Lee, Jhing Fa Wang, Jar Ferr Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In this paper, two hardware-oriented fast motion estimation algorithms and their implementations into a 2-D systolic array for variable block size motion estimation architecture are presented. Two hardware oriented algorithms are proposed to increase the coding speed and reduce the computation complexity of the fast motion estimation (FME) algorithm. The results show that the proposed FME algorithm can speed up 71% coding time of the original standard with slightly PSNR loss and bit rate increase. Therefore, the hardware architecture designs for the proposed algorithms with considerations of both motion vector cost and the sum of absolute difference (SAD) distortion are implemented. The chip, which is realized in CMOS TSMC 0.13μm 1P8M technology, can be operated at 200MHz with gate count 191k including the memory modules.

Original languageEnglish
Title of host publicationICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings
Pages413-417
Number of pages5
DOIs
Publication statusPublished - 2008 Sep 22
EventICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing - Shanghai, China
Duration: 2008 Jul 72008 Jul 9

Publication series

NameICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings

Other

OtherICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing
Country/TerritoryChina
CityShanghai
Period08-07-0708-07-09

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Vision and Pattern Recognition

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