VLSI architecture designs for effective H.264/AVC variable block-size motion estimation

An Chao Tsai, Kuan I. Lee, Jhing Fa Wang, Jar-Ferr Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In this paper, two hardware-oriented fast motion estimation algorithms and their implementations into a 2-D systolic array for variable block size motion estimation architecture are presented. Two hardware oriented algorithms are proposed to increase the coding speed and reduce the computation complexity of the fast motion estimation (FME) algorithm. The results show that the proposed FME algorithm can speed up 71% coding time of the original standard with slightly PSNR loss and bit rate increase. Therefore, the hardware architecture designs for the proposed algorithms with considerations of both motion vector cost and the sum of absolute difference (SAD) distortion are implemented. The chip, which is realized in CMOS TSMC 0.13μm 1P8M technology, can be operated at 200MHz with gate count 191k including the memory modules.

Original languageEnglish
Title of host publicationICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings
Pages413-417
Number of pages5
DOIs
Publication statusPublished - 2008 Sep 22
EventICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing - Shanghai, China
Duration: 2008 Jul 72008 Jul 9

Publication series

NameICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings

Other

OtherICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing
CountryChina
CityShanghai
Period08-07-0708-07-09

Fingerprint

Motion estimation
Hardware
Systolic arrays
Data storage equipment
Costs

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Vision and Pattern Recognition

Cite this

Tsai, A. C., Lee, K. I., Wang, J. F., & Yang, J-F. (2008). VLSI architecture designs for effective H.264/AVC variable block-size motion estimation. In ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings (pp. 413-417). [4590044] (ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings). https://doi.org/10.1109/ICALIP.2008.4590044
Tsai, An Chao ; Lee, Kuan I. ; Wang, Jhing Fa ; Yang, Jar-Ferr. / VLSI architecture designs for effective H.264/AVC variable block-size motion estimation. ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings. 2008. pp. 413-417 (ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings).
@inproceedings{e173c2bc047945dd932e0a5ec5e0fcdb,
title = "VLSI architecture designs for effective H.264/AVC variable block-size motion estimation",
abstract = "In this paper, two hardware-oriented fast motion estimation algorithms and their implementations into a 2-D systolic array for variable block size motion estimation architecture are presented. Two hardware oriented algorithms are proposed to increase the coding speed and reduce the computation complexity of the fast motion estimation (FME) algorithm. The results show that the proposed FME algorithm can speed up 71{\%} coding time of the original standard with slightly PSNR loss and bit rate increase. Therefore, the hardware architecture designs for the proposed algorithms with considerations of both motion vector cost and the sum of absolute difference (SAD) distortion are implemented. The chip, which is realized in CMOS TSMC 0.13μm 1P8M technology, can be operated at 200MHz with gate count 191k including the memory modules.",
author = "Tsai, {An Chao} and Lee, {Kuan I.} and Wang, {Jhing Fa} and Jar-Ferr Yang",
year = "2008",
month = "9",
day = "22",
doi = "10.1109/ICALIP.2008.4590044",
language = "English",
isbn = "9781424417230",
series = "ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings",
pages = "413--417",
booktitle = "ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings",

}

Tsai, AC, Lee, KI, Wang, JF & Yang, J-F 2008, VLSI architecture designs for effective H.264/AVC variable block-size motion estimation. in ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings., 4590044, ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings, pp. 413-417, ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Shanghai, China, 08-07-07. https://doi.org/10.1109/ICALIP.2008.4590044

VLSI architecture designs for effective H.264/AVC variable block-size motion estimation. / Tsai, An Chao; Lee, Kuan I.; Wang, Jhing Fa; Yang, Jar-Ferr.

ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings. 2008. p. 413-417 4590044 (ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - VLSI architecture designs for effective H.264/AVC variable block-size motion estimation

AU - Tsai, An Chao

AU - Lee, Kuan I.

AU - Wang, Jhing Fa

AU - Yang, Jar-Ferr

PY - 2008/9/22

Y1 - 2008/9/22

N2 - In this paper, two hardware-oriented fast motion estimation algorithms and their implementations into a 2-D systolic array for variable block size motion estimation architecture are presented. Two hardware oriented algorithms are proposed to increase the coding speed and reduce the computation complexity of the fast motion estimation (FME) algorithm. The results show that the proposed FME algorithm can speed up 71% coding time of the original standard with slightly PSNR loss and bit rate increase. Therefore, the hardware architecture designs for the proposed algorithms with considerations of both motion vector cost and the sum of absolute difference (SAD) distortion are implemented. The chip, which is realized in CMOS TSMC 0.13μm 1P8M technology, can be operated at 200MHz with gate count 191k including the memory modules.

AB - In this paper, two hardware-oriented fast motion estimation algorithms and their implementations into a 2-D systolic array for variable block size motion estimation architecture are presented. Two hardware oriented algorithms are proposed to increase the coding speed and reduce the computation complexity of the fast motion estimation (FME) algorithm. The results show that the proposed FME algorithm can speed up 71% coding time of the original standard with slightly PSNR loss and bit rate increase. Therefore, the hardware architecture designs for the proposed algorithms with considerations of both motion vector cost and the sum of absolute difference (SAD) distortion are implemented. The chip, which is realized in CMOS TSMC 0.13μm 1P8M technology, can be operated at 200MHz with gate count 191k including the memory modules.

UR - http://www.scopus.com/inward/record.url?scp=51849152990&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51849152990&partnerID=8YFLogxK

U2 - 10.1109/ICALIP.2008.4590044

DO - 10.1109/ICALIP.2008.4590044

M3 - Conference contribution

SN - 9781424417230

T3 - ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings

SP - 413

EP - 417

BT - ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings

ER -

Tsai AC, Lee KI, Wang JF, Yang J-F. VLSI architecture designs for effective H.264/AVC variable block-size motion estimation. In ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings. 2008. p. 413-417. 4590044. (ICALIP 2008 - 2008 International Conference on Audio, Language and Image Processing, Proceedings). https://doi.org/10.1109/ICALIP.2008.4590044