Investigation of efficient iterative decoder realizations is particularly important because the underlying decoding algorithms usually lead to very complicated implementation. This paper describes a VLSI architectural design and analysis of sliding-window Log-MAP decoders in terms of a set of parameters. The derived mathematical representations can be applied to construct a variety of VLSI architectures for different applications. Based on our development, a sliding-window Log-MAP decoder complying with the specification of third-generation mobile cellular systems is realized to demonstrate the performance trade-offs among latency, average decoding rate, area/computation complexity, and memory power consumption. This work thus provides useful and general information on practical implementation of SW-Log-MAP decoders.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2004 Sep 7|
|Event||2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: 2004 May 23 → 2004 May 26
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering