VLSI architecture for modified frequency sensitive self-organizing neural network for image data compression

Lih-Yih Chiou, Jimmy Limqueco, M. A. Bayoumi

Research output: Contribution to conferencePaper

Abstract

We present an adaptive neural network processor for image compression based on a modified frequency-sensitive self-organization algorithm. In this algorithm updating the codevector has a complexity of O(1) and O(N) for best case and worst case situations respectively. Experiments have shown that the worst case situation occurs only at the beginning stage of the learning process. The performance improves as the learning continues. Also the utilization of learning neurons has been considerably increased compared to other algorithm. This algorithm not only achieves a near-optimal result which is comparable with Linde-Buzo-Gray (LBG), but also retains the simplicity for hardware implementation. A mixed-signal architecture is proposed for this algorithm. It consists of analog circuitry which is responsible for neutral network computation and digital circuitry for frequency updating and losers selection.

Original languageEnglish
Pages418-424
Number of pages7
Publication statusPublished - 1994 Dec 1
EventProceedings of the 1994 IEEE International Workshop VLSI Signal Processing - La Jolla, CA, USA
Duration: 1994 Oct 261994 Oct 28

Other

OtherProceedings of the 1994 IEEE International Workshop VLSI Signal Processing
CityLa Jolla, CA, USA
Period94-10-2694-10-28

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All Science Journal Classification (ASJC) codes

  • Signal Processing

Cite this

Chiou, L-Y., Limqueco, J., & Bayoumi, M. A. (1994). VLSI architecture for modified frequency sensitive self-organizing neural network for image data compression. 418-424. Paper presented at Proceedings of the 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA, .