VLSI architecture of extended in-place path metric update for Viterbi decoders

Chien Ming Wu, Ming Der Shieh, Chien Hsing Wu, Ming Hwa Sheu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Efficient memory management is always the key technique for successfully designing the Viterbi decoders. In this paper, a novel and efficient in-place scheduling approach of path metric update and its hardware implementation are developed to increase the equivalent memory bandwidth with limited hardware overhead. The resulting architecture has the following characteristics: (I) The whole memory call be systematically partitioned into several sets of banks and each set can be treated as a local memory of a specific add compare select (ACS) unit. (II) The interconnects between the memory banks and ACS units as well as those between adjacent ACS units an regular and simple such that it is very suitable for VLSI array implementation. Our approach can not only provide a methodology for designing high-performance Viterbi decoders, but also give the trade-off between hardware requirement and computation time for updating path metrics, especially for the convolutional code with larger memory order.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages206-209
Number of pages4
DOIs
Publication statusPublished - 2001 Dec 1
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 2001 May 62001 May 9

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume4

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period01-05-0601-05-09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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