VLSI architecture of extended in-place path metric update for Viterbi decoders

C. M. Wu, Ming-Der Shieh, C. H. Wu, M. H. Sheu

Research output: Contribution to journalConference article

Abstract

Efficient memory management is always the key technique for successfully designing the Viterbi decoders. In this paper, a novel and efficient in-place scheduling approach of path metric update and its hardware implementation are developed to increase the equivalent memory bandwidth with limited hardware overhead. The resulting architecture has the following characteristics: (I) The whole memory can be systematically partitioned into several sets of banks and each set can be treated as a local memory of a specific add_compare_select (ACS) unit. (II) The interconnects between the memory banks and ACS units as well as those between adjacent ACS traits are regular and simple such that it is very suitable for VLSI array implementation. Our approach can not only provide a methodology for designing high-performance Viterbi decoders, but also give the trade-off between hardware requirement and computation time for updating path metrics, especially for the convolutional code with larger memory order.

Original languageEnglish
JournalMaterials Research Society Symposium - Proceedings
Volume626
Publication statusPublished - 2001 Jan 1
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 2000 Apr 242000 Apr 27

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Viterbi decoders
very large scale integration
Data storage equipment
hardware
Computer hardware
Convolutional codes
scheduling
Scheduling
methodology
bandwidth
Hardware
Bandwidth
requirements

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanics of Materials
  • Mechanical Engineering

Cite this

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title = "VLSI architecture of extended in-place path metric update for Viterbi decoders",
abstract = "Efficient memory management is always the key technique for successfully designing the Viterbi decoders. In this paper, a novel and efficient in-place scheduling approach of path metric update and its hardware implementation are developed to increase the equivalent memory bandwidth with limited hardware overhead. The resulting architecture has the following characteristics: (I) The whole memory can be systematically partitioned into several sets of banks and each set can be treated as a local memory of a specific add_compare_select (ACS) unit. (II) The interconnects between the memory banks and ACS units as well as those between adjacent ACS traits are regular and simple such that it is very suitable for VLSI array implementation. Our approach can not only provide a methodology for designing high-performance Viterbi decoders, but also give the trade-off between hardware requirement and computation time for updating path metrics, especially for the convolutional code with larger memory order.",
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VLSI architecture of extended in-place path metric update for Viterbi decoders. / Wu, C. M.; Shieh, Ming-Der; Wu, C. H.; Sheu, M. H.

In: Materials Research Society Symposium - Proceedings, Vol. 626, 01.01.2001.

Research output: Contribution to journalConference article

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