VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem

Che Han Wu, Ming-Der Shieh, Chien Hsing Wu, Ming Hwa Sheu, Jia Lin Sheu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a high-radix modular multiplication algorithm and its corresponding VLSI architecture for RSA cryptosystem. To reduce the total number of required operations, we partition the multiplier operand into several equal-sized segments and treat each segment as a basic unit for accumulation and modulo operations. Then, the multiplication and residue calculation of each segment are performed in a pipelined fashion to increase the throughput rate. This paper also shows how to simplify the quotient estimation based on multiple-bit overlapping scanning and to reduce the logic depth in high-radix implementation. Results show that only a small lookup table is needed for quotient estimation in our development and the total operating time is smaller than that of the corresponding radix-2 implementation.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Volume1
ISBN (Print)0780354729
Publication statusPublished - 1999
EventProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA
Duration: 1999 May 301999 Jun 2

Other

OtherProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
CityOrlando, FL, USA
Period99-05-3099-06-02

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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