Abstract
This paper presents a high-radix modular multiplication algorithm and its corresponding VLSI architecture for RSA cryptosystem. To reduce the total number of required operations, we partition the multiplier operand into several equal-sized segments and treat each segment as a basic unit for accumulation and modulo operations. Then, the multiplication and residue calculation of each segment are performed in a pipelined fashion to increase the throughput rate. This paper also shows how to simplify the quotient estimation based on multiple-bit overlapping scanning and to reduce the logic depth in high-radix implementation. Results show that only a small lookup table is needed for quotient estimation in our development and the total operating time is smaller than that of the corresponding radix-2 implementation.
| Original language | English |
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| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | IEEE |
| Volume | 1 |
| ISBN (Print) | 0780354729 |
| Publication status | Published - 1999 |
| Event | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA Duration: 1999 May 30 → 1999 Jun 2 |
Other
| Other | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 |
|---|---|
| City | Orlando, FL, USA |
| Period | 99-05-30 → 99-06-02 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering