VLSI architecture of polynomial multiplication for BGV fully homomorphic encryption

Hsuan Jui Hsu, Ming Der Shieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Fully homomorphic encryption (FHE) has attracted much attention because computations can be directly performed on ciphertexts. This work explores the hardware architecture of polynomial multiplication defined in BGV-FHE, targeting the applications of aggregate plaintext using cyclotomic polynomials. We show how to effectively combine the characteristics of cyclotomic polynomials and the prime-factor FFT algorithm to obtain a novel design derived by the concept of Chinese Remainder Theorem. Experimental results reveal that a significant speedup in terms of operation reduction can be achieved by adopting the proposed schemes as compared to existing works assuming a comparable security level. For example, about 2.44 and 6.34 times improvement in the total number of required modular addition and multiplication, respectively, can be obtained by using 32 one-bit aggregate slots as compared to Chen's work when the 21845-th cyclotomic polynomial is considered. The improvement could be huge if all of the available slots are involved in applications.

Original languageEnglish
Title of host publication2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728133201
Publication statusPublished - 2020
Event52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online
Duration: 2020 Oct 102020 Oct 21

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2020-October
ISSN (Print)0271-4310

Conference

Conference52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
CityVirtual, Online
Period20-10-1020-10-21

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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