VLSI design of a high speed pipelined Reed-Solomon CODEC

C.-T. Huang, Cheng-Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationInternational Symposium on Multi-Technology Information Processing (ISMIP)
Place of PublicationHsinchu
Pages517-522
Publication statusPublished - 1996 Dec

Cite this

Huang, C-T., & Wu, C-W. (1996). VLSI design of a high speed pipelined Reed-Solomon CODEC. In International Symposium on Multi-Technology Information Processing (ISMIP) (pp. 517-522). Hsinchu.
Huang, C.-T. ; Wu, Cheng-Wen. / VLSI design of a high speed pipelined Reed-Solomon CODEC. International Symposium on Multi-Technology Information Processing (ISMIP). Hsinchu, 1996. pp. 517-522
@inproceedings{71206003918748c7a2e5a3fe50780345,
title = "VLSI design of a high speed pipelined Reed-Solomon CODEC",
author = "C.-T. Huang and Cheng-Wen Wu",
year = "1996",
month = "12",
language = "English",
pages = "517--522",
booktitle = "International Symposium on Multi-Technology Information Processing (ISMIP)",

}

Huang, C-T & Wu, C-W 1996, VLSI design of a high speed pipelined Reed-Solomon CODEC. in International Symposium on Multi-Technology Information Processing (ISMIP). Hsinchu, pp. 517-522.

VLSI design of a high speed pipelined Reed-Solomon CODEC. / Huang, C.-T.; Wu, Cheng-Wen.

International Symposium on Multi-Technology Information Processing (ISMIP). Hsinchu, 1996. p. 517-522.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - VLSI design of a high speed pipelined Reed-Solomon CODEC

AU - Huang, C.-T.

AU - Wu, Cheng-Wen

PY - 1996/12

Y1 - 1996/12

M3 - Conference contribution

SP - 517

EP - 522

BT - International Symposium on Multi-Technology Information Processing (ISMIP)

CY - Hsinchu

ER -

Huang C-T, Wu C-W. VLSI design of a high speed pipelined Reed-Solomon CODEC. In International Symposium on Multi-Technology Information Processing (ISMIP). Hsinchu. 1996. p. 517-522