VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes

Ming-Der Shieh, Shih Hao Fang, Shing Chung Tang, Der Wei Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2011
Pages242-246
Number of pages5
DOIs
Publication statusPublished - 2011 Dec 28
Event24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan
Duration: 2011 Sep 262011 Sep 28

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Other

Other24th IEEE International System on Chip Conference, SOCC 2011
CountryTaiwan
CityTaipei
Period11-09-2611-09-28

Fingerprint

Data storage equipment
Computer peripheral equipment

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Shieh, M-D., Fang, S. H., Tang, S. C., & Yang, D. W. (2011). VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes. In Proceedings - IEEE International SOC Conference, SOCC 2011 (pp. 242-246). [6085108] (International System on Chip Conference). https://doi.org/10.1109/SOCC.2011.6085108
Shieh, Ming-Der ; Fang, Shih Hao ; Tang, Shing Chung ; Yang, Der Wei. / VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes. Proceedings - IEEE International SOC Conference, SOCC 2011. 2011. pp. 242-246 (International System on Chip Conference).
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Shieh, M-D, Fang, SH, Tang, SC & Yang, DW 2011, VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes. in Proceedings - IEEE International SOC Conference, SOCC 2011., 6085108, International System on Chip Conference, pp. 242-246, 24th IEEE International System on Chip Conference, SOCC 2011, Taipei, Taiwan, 11-09-26. https://doi.org/10.1109/SOCC.2011.6085108

VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes. / Shieh, Ming-Der; Fang, Shih Hao; Tang, Shing Chung; Yang, Der Wei.

Proceedings - IEEE International SOC Conference, SOCC 2011. 2011. p. 242-246 6085108 (International System on Chip Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Shieh M-D, Fang SH, Tang SC, Yang DW. VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes. In Proceedings - IEEE International SOC Conference, SOCC 2011. 2011. p. 242-246. 6085108. (International System on Chip Conference). https://doi.org/10.1109/SOCC.2011.6085108