TY - GEN
T1 - VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes
AU - Shieh, Ming-Der
AU - Fang, Shih Hao
AU - Tang, Shing Chung
AU - Yang, Der Wei
PY - 2011/12/28
Y1 - 2011/12/28
N2 - This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.
AB - This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.
UR - http://www.scopus.com/inward/record.url?scp=84255175749&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84255175749&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2011.6085108
DO - 10.1109/SOCC.2011.6085108
M3 - Conference contribution
AN - SCOPUS:84255175749
SN - 9781457716164
T3 - International System on Chip Conference
SP - 242
EP - 246
BT - Proceedings - IEEE International SOC Conference, SOCC 2011
T2 - 24th IEEE International System on Chip Conference, SOCC 2011
Y2 - 26 September 2011 through 28 September 2011
ER -