VLSI design of the RSA public-key cryptosystem

Shyue Kung Lu, Cheng Wen Wu

Research output: Contribution to conferencePaperpeer-review

Abstract

In order to achieve sufficient security in a public-key cryptosystem, the numbers involved are very large (200 digits or more in length). Hardware implementation of the RSA system therefore is challenging. In this paper an RSA cryptosystem is proposed. The core modular multi plication operation is implemented with a block multiplier module, a modulus coefficient module and a mod-N module. Finally, an RSA coefficient module is used to accommodate the modular exponentiation of the RSA cryptosystem which is implemented on the host computer. Our approach avoids the high cost of a pure parallel design and the low speed of a pure serial one. For 512-bit words and a 100 MHz clock, the baud rate will be about 100K bits per second.

Original languageEnglish
Pages68-71
Number of pages4
Publication statusPublished - 1997 Dec 1
Event7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore
Duration: 1997 Sep 101997 Sep 12

Other

Other7th International Symposium on IC Technology, Systems and Applications ISIC 97
CountrySingapore
CitySingapore
Period97-09-1097-09-12

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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