The lifting scheme has been developed as a flexible tool suitable for constructing biorthogonal wavelets recently. In this paper, we present an efficient VLSI architecture for the implementation of 1D lifting discrete wavelet transform. The architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Because of its modular, regular, and flexible structure, the design is scalable for different resolution levels. In addition, its area is independent of the length of the 1D input sequence and its latency is independent of the number of resolution levels. Since the architecture has a similar topology to a scan chain, we can modify it easily to become a testable scan-based design by adding very few hardware resources. For the computations of N-sample 1D k-level analysis (5, 3) lifting wavelet transform, the design takes N+1 clock cycles, and requires two multipliers, four adders, and (3 + 2.25 × 2k) registers. In the simulation, it works with a clock period of 10 ns and achieves a processing rate of about 100 × 106 samples/sec for k-level lifting wavelet transform.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics