VLSI implementation of an edge-oriented image scaling processor

Pei Yin Chen; Chih Yuan Lien; Chi Pin Lu

doi:10.1109/TVLSI.2008.2003003

VLSI implementation of an edge-oriented image scaling processor

Pei Yin Chen, Chih Yuan Lien, Chi Pin Lu

Department of Computer Science and Information Engineering

Research output: Contribution to journal › Article › peer-review

48 Citations (Scopus)

Abstract

Image scaling is a very important technique and has been widely used in many image processing applications. In this paper, we present an edge-oriented area-pixel scaling processor. To achieve the goal of low cost, the area-pixel scaling technique is implemented with a low-complexity VLSI architecture in our design. A simple edge catching technique is adopted to preserve the image edge features effectively so as to achieve better image quality. Compared with the previous low-complexity techniques, our method performs better in terms of both quantitative evaluation and visual quality. The seven-stage VLSI architecture of our image scaling processor contains 10.4-K gate counts and yields a processing rate of about 200 MHz by using TSMC 0.18-$\mu$m technology.

Original language	English
Article number	4799222
Pages (from-to)	1275-1284
Number of pages	10
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	17
Issue number	9
DOIs	https://doi.org/10.1109/TVLSI.2008.2003003
Publication status	Published - 2009 Sept

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2008.2003003

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title = "VLSI implementation of an edge-oriented image scaling processor",

abstract = "Image scaling is a very important technique and has been widely used in many image processing applications. In this paper, we present an edge-oriented area-pixel scaling processor. To achieve the goal of low cost, the area-pixel scaling technique is implemented with a low-complexity VLSI architecture in our design. A simple edge catching technique is adopted to preserve the image edge features effectively so as to achieve better image quality. Compared with the previous low-complexity techniques, our method performs better in terms of both quantitative evaluation and visual quality. The seven-stage VLSI architecture of our image scaling processor contains 10.4-K gate counts and yields a processing rate of about 200 MHz by using TSMC 0.18-$\mu$m technology.",

author = "Chen, {Pei Yin} and Lien, {Chih Yuan} and Lu, {Chi Pin}",

note = "Funding Information: Manuscript received January 11, 2008; revised May 26, 2008. First published March 10, 2009; current version published August 19, 2009. This work was supported in part by the National Science Council, Taiwan, under Grant NSC-96-2221-E-006-027-MY3. Also, this work made use of Shared Facilities supported by the Program of Top 100 Universities Advancement, Ministry of Education, Taiwan.",

year = "2009",

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doi = "10.1109/TVLSI.2008.2003003",

language = "English",

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PY - 2009/9

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N2 - Image scaling is a very important technique and has been widely used in many image processing applications. In this paper, we present an edge-oriented area-pixel scaling processor. To achieve the goal of low cost, the area-pixel scaling technique is implemented with a low-complexity VLSI architecture in our design. A simple edge catching technique is adopted to preserve the image edge features effectively so as to achieve better image quality. Compared with the previous low-complexity techniques, our method performs better in terms of both quantitative evaluation and visual quality. The seven-stage VLSI architecture of our image scaling processor contains 10.4-K gate counts and yields a processing rate of about 200 MHz by using TSMC 0.18-$\mu$m technology.

AB - Image scaling is a very important technique and has been widely used in many image processing applications. In this paper, we present an edge-oriented area-pixel scaling processor. To achieve the goal of low cost, the area-pixel scaling technique is implemented with a low-complexity VLSI architecture in our design. A simple edge catching technique is adopted to preserve the image edge features effectively so as to achieve better image quality. Compared with the previous low-complexity techniques, our method performs better in terms of both quantitative evaluation and visual quality. The seven-stage VLSI architecture of our image scaling processor contains 10.4-K gate counts and yields a processing rate of about 200 MHz by using TSMC 0.18-$\mu$m technology.

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VLSI implementation of an edge-oriented image scaling processor

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