In this paper, we propose the pipelined VLSI architecture and modular design to realize the coefficient-by-coefficient two-dimensional inverse discrete cosine transform (2-D IDCT) suggested by . Based on parallel processing, the architecture of this chip is designed with a five-stage pipeline to meet the speed requirement for real-time applications. The key building modules of this chip include a generator of cosine angle index, a pipelined multiplier, and a matrix accumulator core. Satisfying the IEEE standard of 2-D IDCT in computational accuracy, this realized IDCT chip, which can work at a clock rate of higher than 50 MHz, is implemented by the CMOS technology in a reasonable die size. With modular and regular structures, the IDCT VLSI chip can be operated in progressive transform. In a real video decoding system, the average pixel-rate of the proposed 2-D IDCT chip achieves over 150 MHz for decoding intraframes and up to 400 MHz for decoding interframes.
|Number of pages||11|
|Journal||IEEE Transactions on Circuits and Systems for Video Technology|
|Publication status||Published - 1995 Oct|
All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering