VLSI Implementation of Parallel Coefficient-by-Coefficient Two-Dimensional IDCT Processor

Shih Chang Hsia, Bin-Da Liu, Jar-Ferr Yang

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

In this paper, we propose the pipelined VLSI architecture and modular design to realize the coefficient-by-coefficient two-dimensional inverse discrete cosine transform (2-D IDCT) suggested by [1]. Based on parallel processing, the architecture of this chip is designed with a five-stage pipeline to meet the speed requirement for real-time applications. The key building modules of this chip include a generator of cosine angle index, a pipelined multiplier, and a matrix accumulator core. Satisfying the IEEE standard of 2-D IDCT in computational accuracy, this realized IDCT chip, which can work at a clock rate of higher than 50 MHz, is implemented by the CMOS technology in a reasonable die size. With modular and regular structures, the IDCT VLSI chip can be operated in progressive transform. In a real video decoding system, the average pixel-rate of the proposed 2-D IDCT chip achieves over 150 MHz for decoding intraframes and up to 400 MHz for decoding interframes.

Original languageEnglish
Pages (from-to)396-406
Number of pages11
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume5
Issue number5
DOIs
Publication statusPublished - 1995 Jan 1

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Decoding
Discrete cosine transforms
Clocks
Pipelines
Pixels
Processing

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Electrical and Electronic Engineering

Cite this

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abstract = "In this paper, we propose the pipelined VLSI architecture and modular design to realize the coefficient-by-coefficient two-dimensional inverse discrete cosine transform (2-D IDCT) suggested by [1]. Based on parallel processing, the architecture of this chip is designed with a five-stage pipeline to meet the speed requirement for real-time applications. The key building modules of this chip include a generator of cosine angle index, a pipelined multiplier, and a matrix accumulator core. Satisfying the IEEE standard of 2-D IDCT in computational accuracy, this realized IDCT chip, which can work at a clock rate of higher than 50 MHz, is implemented by the CMOS technology in a reasonable die size. With modular and regular structures, the IDCT VLSI chip can be operated in progressive transform. In a real video decoding system, the average pixel-rate of the proposed 2-D IDCT chip achieves over 150 MHz for decoding intraframes and up to 400 MHz for decoding interframes.",
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VLSI Implementation of Parallel Coefficient-by-Coefficient Two-Dimensional IDCT Processor. / Hsia, Shih Chang; Liu, Bin-Da; Yang, Jar-Ferr.

In: IEEE Transactions on Circuits and Systems for Video Technology, Vol. 5, No. 5, 01.01.1995, p. 396-406.

Research output: Contribution to journalArticle

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