Voltage island-driven floorplanning considering level shifter placement

Jai Ming Lin, Wei Yi Cheng, Chung Lin Lee, Richard C.J. Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Low power has become a burning issue in modern VLSI design. To deal with this problem, the multiple-supply voltage (MSV) is a technique widely applied to a design to reduce its power consumption. However, there exist several challenges in implementing Multi-Voltage designs, which includes floorplanning, level-shifter placement, and power planning [5]. Among these challenges, placement of level shifters has direct impacts on the chip area, total wirelength, and power planning. Although several works considering MSV driven floorplanning have been proposed, they do not actually place level shifters in their flows, which makes their results unrealistic. Yu et al. [19] first proposed a methodology to place level shifters during floorplanning. But, level shifters are inserted in the whitespace of a chip, which would increase wirelength of long wires and make power planning more difficult. Thus, in this paper, we first propose two ways to allocate regions for level shifters during floorplanning, and then give a two-stage approach to place these level shifters at proper locations. The experimental results reveal that the wirelength is underestimated if we do place level shifters and it can obtain smaller wirelength if we can consider level shifters during floorplanning.

Original languageEnglish
Title of host publicationASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages443-448
Number of pages6
DOIs
Publication statusPublished - 2012 Apr 26
Event17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia
Duration: 2012 Jan 302012 Feb 2

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
CountryAustralia
CitySydney, NSW
Period12-01-3012-02-02

Fingerprint

Planning
Electric potential
Electric power utilization
Wire

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Lin, J. M., Cheng, W. Y., Lee, C. L., & Hsu, R. C. J. (2012). Voltage island-driven floorplanning considering level shifter placement. In ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference (pp. 443-448). [6164989] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2012.6164989
Lin, Jai Ming ; Cheng, Wei Yi ; Lee, Chung Lin ; Hsu, Richard C.J. / Voltage island-driven floorplanning considering level shifter placement. ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. 2012. pp. 443-448 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
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Lin, JM, Cheng, WY, Lee, CL & Hsu, RCJ 2012, Voltage island-driven floorplanning considering level shifter placement. in ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference., 6164989, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 443-448, 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, NSW, Australia, 12-01-30. https://doi.org/10.1109/ASPDAC.2012.6164989

Voltage island-driven floorplanning considering level shifter placement. / Lin, Jai Ming; Cheng, Wei Yi; Lee, Chung Lin; Hsu, Richard C.J.

ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. 2012. p. 443-448 6164989 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lin JM, Cheng WY, Lee CL, Hsu RCJ. Voltage island-driven floorplanning considering level shifter placement. In ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. 2012. p. 443-448. 6164989. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2012.6164989