Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

P. J. Sung; C. Y. Chang; L. Y. Chen; K. H. Kao; C. J. Su; T. H. Liao; C. C. Fang; C. J. Wang; T. C. Hong; C. Y. Jao; H. S. Hsu; S. X. Luo; Y. S. Wang; H. F. Huang; J. H. Li; Y. C. Huang; F. K. Hsueh; C. T. Wu; Y. M. Huang; F. J. Hou; G. L. Luo; Y. C. Huang; Y. L. Shen; W. C.Y. Ma; K. P. Huang; K. L. Lin; S. Samukawa; Y. Li; G. W. Huang; Y. J. Lee; J. Y. Li; W. F. Wu; J. M. Shieh; T. S. Chao; W. K. Yeh; Y. H. Wang

doi:10.1109/IEDM.2018.8614553

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

P. J. Sung, C. Y. Chang, L. Y. Chen, K. H. Kao, C. J. Su, T. H. Liao, C. C. Fang, C. J. Wang, T. C. Hong, C. Y. Jao, H. S. Hsu, S. X. Luo, Y. S. Wang, H. F. Huang, J. H. Li, Y. C. Huang, F. K. Hsueh, C. T. Wu, Y. M. Huang, F. J. HouG. L. Luo, Y. C. Huang, Y. L. Shen, W. C.Y. Ma, K. P. Huang, K. L. Lin, S. Samukawa, Y. Li, G. W. Huang, Y. J. Lee, J. Y. Li, W. F. Wu, J. M. Shieh, T. S. Chao, W. K. Yeh, Y. H. Wang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Citations (Scopus)

Abstract

For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 °C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.

Original language	English
Title of host publication	2018 IEEE International Electron Devices Meeting, IEDM 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	21.4.1-21.4.4
ISBN (Electronic)	9781728119878
DOIs	https://doi.org/10.1109/IEDM.2018.8614553
Publication status	Published - 2018 Jul 2
Event	64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States Duration: 2018 Dec 1 → 2018 Dec 5

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2018-December
ISSN (Print)	0163-1918

Conference

Conference	64th Annual IEEE International Electron Devices Meeting, IEDM 2018
Country/Territory	United States
City	San Francisco
Period	18-12-01 → 18-12-05

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM.2018.8614553

Cite this

Sung, P. J., Chang, C. Y., Chen, L. Y., Kao, K. H., Su, C. J., Liao, T. H., Fang, C. C., Wang, C. J., Hong, T. C., Jao, C. Y., Hsu, H. S., Luo, S. X., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Huang, Y. M., ... Wang, Y. H. (2018). Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications. In 2018 IEEE International Electron Devices Meeting, IEDM 2018 (pp. 21.4.1-21.4.4). Article 8614553 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614553

Sung, P. J. ; Chang, C. Y. ; Chen, L. Y. et al. / Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications. 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 21.4.1-21.4.4 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{25ec74c4be9a4be08159e30a75b50211,

title = "Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications",

abstract = "For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 °C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.",

author = "Sung, \{P. J.\} and Chang, \{C. Y.\} and Chen, \{L. Y.\} and Kao, \{K. H.\} and Su, \{C. J.\} and Liao, \{T. H.\} and Fang, \{C. C.\} and Wang, \{C. J.\} and Hong, \{T. C.\} and Jao, \{C. Y.\} and Hsu, \{H. S.\} and Luo, \{S. X.\} and Wang, \{Y. S.\} and Huang, \{H. F.\} and Li, \{J. H.\} and Huang, \{Y. C.\} and Hsueh, \{F. K.\} and Wu, \{C. T.\} and Huang, \{Y. M.\} and Hou, \{F. J.\} and Luo, \{G. L.\} and Huang, \{Y. C.\} and Shen, \{Y. L.\} and Ma, \{W. C.Y.\} and Huang, \{K. P.\} and Lin, \{K. L.\} and S. Samukawa and Y. Li and Huang, \{G. W.\} and Lee, \{Y. J.\} and Li, \{J. Y.\} and Wu, \{W. F.\} and Shieh, \{J. M.\} and Chao, \{T. S.\} and Yeh, \{W. K.\} and Wang, \{Y. H.\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 ; Conference date: 01-12-2018 Through 05-12-2018",

year = "2018",

month = jul,

day = "2",

doi = "10.1109/IEDM.2018.8614553",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "21.4.1--21.4.4",

booktitle = "2018 IEEE International Electron Devices Meeting, IEDM 2018",

address = "United States",

}

Sung, PJ, Chang, CY, Chen, LY, Kao, KH, Su, CJ, Liao, TH, Fang, CC, Wang, CJ, Hong, TC, Jao, CY, Hsu, HS, Luo, SX, Wang, YS, Huang, HF, Li, JH, Huang, YC, Hsueh, FK, Wu, CT, Huang, YM, Hou, FJ, Luo, GL, Huang, YC, Shen, YL, Ma, WCY, Huang, KP, Lin, KL, Samukawa, S, Li, Y, Huang, GW, Lee, YJ, Li, JY, Wu, WF, Shieh, JM, Chao, TS, Yeh, WK & Wang, YH 2018, Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications. in 2018 IEEE International Electron Devices Meeting, IEDM 2018., 8614553, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2018-December, Institute of Electrical and Electronics Engineers Inc., pp. 21.4.1-21.4.4, 64th Annual IEEE International Electron Devices Meeting, IEDM 2018, San Francisco, United States, 18-12-01. https://doi.org/10.1109/IEDM.2018.8614553

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications. / Sung, P. J.; Chang, C. Y.; Chen, L. Y. et al.
2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 21.4.1-21.4.4 8614553 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

AU - Sung, P. J.

AU - Chang, C. Y.

AU - Chen, L. Y.

AU - Kao, K. H.

AU - Su, C. J.

AU - Liao, T. H.

AU - Fang, C. C.

AU - Wang, C. J.

AU - Hong, T. C.

AU - Jao, C. Y.

AU - Hsu, H. S.

AU - Luo, S. X.

AU - Wang, Y. S.

AU - Huang, H. F.

AU - Li, J. H.

AU - Huang, Y. C.

AU - Hsueh, F. K.

AU - Wu, C. T.

AU - Huang, Y. M.

AU - Hou, F. J.

AU - Luo, G. L.

AU - Huang, Y. C.

AU - Shen, Y. L.

AU - Ma, W. C.Y.

AU - Huang, K. P.

AU - Lin, K. L.

AU - Samukawa, S.

AU - Li, Y.

AU - Huang, G. W.

AU - Lee, Y. J.

AU - Li, J. Y.

AU - Wu, W. F.

AU - Shieh, J. M.

AU - Chao, T. S.

AU - Yeh, W. K.

AU - Wang, Y. H.

PY - 2018/7/2

Y1 - 2018/7/2

N2 - For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 °C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.

AB - For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 °C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.

UR - https://www.scopus.com/pages/publications/85061775176

UR - https://www.scopus.com/inward/citedby.url?scp=85061775176&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2018.8614553

DO - 10.1109/IEDM.2018.8614553

M3 - Conference contribution

AN - SCOPUS:85061775176

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 21.4.1-21.4.4

BT - 2018 IEEE International Electron Devices Meeting, IEDM 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 64th Annual IEEE International Electron Devices Meeting, IEDM 2018

Y2 - 1 December 2018 through 5 December 2018

ER -

Sung PJ, Chang CY, Chen LY, Kao KH, Su CJ, Liao TH et al. Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications. In 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 21.4.1-21.4.4. 8614553. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2018.8614553

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

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