Wake-up logic optimizations through selective match and wakeup range limitation

Kuo Su Hsiao, Chung-Ho Chen

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper presents two effective wakeup designs that improve the speed, power, area, and scalability without instructions per cycle (IPC) loss for dynamic instruction schedulers. First, a wakeup design is proposed to aim at reducing the power consumption and wakeup latency. This design removes the READ of the destination tags from the wakeup path by matching the source tags directly with the grant lines. Moreover, this design eliminates the redundant matches during the wakeup operations by matching the source tags with only the selected grant lines. Next, the second design explores a metric called wakeup locality to further reduce the area cost of the wakeup logic. By limiting the wakeup ranges for the instructions in the issue window, this design not only reduces the area requirement but also improves the scalability. The experimental results show that this range-limited-wakeup design saves 76%-94% of the power consumption and reduces 29%-77% in the wakeup latency compared to the conventional CAM-based scheme with only 5%-44% of the area cost in a traditional RAM-based scheme. The results also show that this design scales well with the increase of both the issue width and the window size.

Original languageEnglish
Article number1715346
Pages (from-to)1089-1102
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume14
Issue number10
DOIs
Publication statusPublished - 2006 Oct 1

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Scalability
Electric power utilization
Random access storage
Computer aided manufacturing
Costs

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

@article{e06e52fd66094dd0ae90f64b45fe7ee4,
title = "Wake-up logic optimizations through selective match and wakeup range limitation",
abstract = "This paper presents two effective wakeup designs that improve the speed, power, area, and scalability without instructions per cycle (IPC) loss for dynamic instruction schedulers. First, a wakeup design is proposed to aim at reducing the power consumption and wakeup latency. This design removes the READ of the destination tags from the wakeup path by matching the source tags directly with the grant lines. Moreover, this design eliminates the redundant matches during the wakeup operations by matching the source tags with only the selected grant lines. Next, the second design explores a metric called wakeup locality to further reduce the area cost of the wakeup logic. By limiting the wakeup ranges for the instructions in the issue window, this design not only reduces the area requirement but also improves the scalability. The experimental results show that this range-limited-wakeup design saves 76{\%}-94{\%} of the power consumption and reduces 29{\%}-77{\%} in the wakeup latency compared to the conventional CAM-based scheme with only 5{\%}-44{\%} of the area cost in a traditional RAM-based scheme. The results also show that this design scales well with the increase of both the issue width and the window size.",
author = "Hsiao, {Kuo Su} and Chung-Ho Chen",
year = "2006",
month = "10",
day = "1",
doi = "10.1109/TVLSI.2006.884150",
language = "English",
volume = "14",
pages = "1089--1102",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

Wake-up logic optimizations through selective match and wakeup range limitation. / Hsiao, Kuo Su; Chen, Chung-Ho.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 10, 1715346, 01.10.2006, p. 1089-1102.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Wake-up logic optimizations through selective match and wakeup range limitation

AU - Hsiao, Kuo Su

AU - Chen, Chung-Ho

PY - 2006/10/1

Y1 - 2006/10/1

N2 - This paper presents two effective wakeup designs that improve the speed, power, area, and scalability without instructions per cycle (IPC) loss for dynamic instruction schedulers. First, a wakeup design is proposed to aim at reducing the power consumption and wakeup latency. This design removes the READ of the destination tags from the wakeup path by matching the source tags directly with the grant lines. Moreover, this design eliminates the redundant matches during the wakeup operations by matching the source tags with only the selected grant lines. Next, the second design explores a metric called wakeup locality to further reduce the area cost of the wakeup logic. By limiting the wakeup ranges for the instructions in the issue window, this design not only reduces the area requirement but also improves the scalability. The experimental results show that this range-limited-wakeup design saves 76%-94% of the power consumption and reduces 29%-77% in the wakeup latency compared to the conventional CAM-based scheme with only 5%-44% of the area cost in a traditional RAM-based scheme. The results also show that this design scales well with the increase of both the issue width and the window size.

AB - This paper presents two effective wakeup designs that improve the speed, power, area, and scalability without instructions per cycle (IPC) loss for dynamic instruction schedulers. First, a wakeup design is proposed to aim at reducing the power consumption and wakeup latency. This design removes the READ of the destination tags from the wakeup path by matching the source tags directly with the grant lines. Moreover, this design eliminates the redundant matches during the wakeup operations by matching the source tags with only the selected grant lines. Next, the second design explores a metric called wakeup locality to further reduce the area cost of the wakeup logic. By limiting the wakeup ranges for the instructions in the issue window, this design not only reduces the area requirement but also improves the scalability. The experimental results show that this range-limited-wakeup design saves 76%-94% of the power consumption and reduces 29%-77% in the wakeup latency compared to the conventional CAM-based scheme with only 5%-44% of the area cost in a traditional RAM-based scheme. The results also show that this design scales well with the increase of both the issue width and the window size.

UR - http://www.scopus.com/inward/record.url?scp=33750595071&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33750595071&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2006.884150

DO - 10.1109/TVLSI.2006.884150

M3 - Article

AN - SCOPUS:33750595071

VL - 14

SP - 1089

EP - 1102

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 10

M1 - 1715346

ER -