Warpage simulations with P-V-T-C equation and experiments of fan-out wafer level package after encapsulation process

Shang Shiuan Deng, Sheng-Jye Hwang, Huei-Huang Lee, Durn Yuan Huang, Geng Shin Shen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Wafer level packaging is the technique that encapsulates integrated circuit on the wafer directly and different from the traditional IC package. Comparing with the traditional IC package, wafer level chip scale packaging has several advantages such as: smaller package size (reduce area and thickness), lighter weight, more fabricate simply, better electric performance and cost down. Therefore, the wafer level package is suitable for cell phones, notebooks, handheld computers and digital cameras. In addition, the wafer level package can integrate wafer manufacture, encapsulation and test that simplifies the all production processes. The fan-out wafer level package discussed here has the flip chip form which uses thin-film redistribute then uses solder bump to connect the package to the printed wiring board directly. Liquid compound was used for the encapsulation process. Because the thickness of the fan-out wafer level package is thinner than traditional IC package, so the fan-out wafer level package produced more serious warpage. Warpage plays an important role during integrated circuit encapsulation process and the too large amount of warpage will not proceed to the next manufacture process in this study. Previous researchers had focused on warpage analysis with thermal-induced shrinkage and the cure-induced shrinkage was neglected. However, more and more studies indicated that the prediction of warpage only according to CTE (Coefficient of Thermal Expansion) was not able to accurately predict the amount of warpage in IC packaging. This study used an approach considering both cureand thermal-induced shrinkage during encapsulation process was presented to predict the amount of warpage. The cure-induced shrinkage was described by the pressure-volume-temperature-cure (P-V-T-C) equation of the liquid compound. The thermal-induced shrinkage was described by the coefficients of thermal expansion of the component materials. The liquid compound properties were obtained by various techniques: cure kinetics by differential scanning calorimeter (DSC), cure induced shrinkage by P-V-T-C testing machine. These experimental data were used to formulate the P-V-T-C equation. In this study, fan-out wafer level package was used for the simulation. The simulation results were verified with experiments. It showed that the approach of considering both thermal and cure/compressibility effects could better predict the amount of warpage for fan-out wafer level package. The P-V-T-C equation was successfully implemented and verified that warpage was governed by both thermal shrinkage and cure shrinkage. The amount of warpage after molding could be accurately predicted with this methodology. The simulation results showed that cure shrinkage of liquid compound was the dominant factor for package warpage after encapsulation.

Original languageEnglish
Title of host publicationInternational Microsystems Packaging Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference, Proceedings
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 5th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference - Taipei, Taiwan
Duration: 2010 Oct 202010 Oct 22

Publication series

NameInternational Microsystems Packaging Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference, Proceedings

Other

Other2010 5th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference
CountryTaiwan
CityTaipei
Period10-10-2010-10-22

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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