TY - GEN
T1 - Window architecture for deblocking filter in H.264/AVC
AU - Chen, Chung Ming
AU - Zeng, Jian Ping
AU - Chen, Chung Ho
AU - Yu, Chao Tang
AU - Chang, Yu Pin
PY - 2006/1/1
Y1 - 2006/1/1
N2 - In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a window processing approach with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV, 1920×1080 pixels/frame, 60 frames/s video signals) video operation at 60MHz. Moreover, the memory and system performance of our proposal significantly outperforms the previous designs as shown in result section.
AB - In this paper, we study and analyze the computational complexity of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result shows that the memory reference, content activity check operations and filter operations are known to be very time consuming in the decoder of this new video coding standard. In order to improve overall system performance, we propose a window processing approach with efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV, 1920×1080 pixels/frame, 60 frames/s video signals) video operation at 60MHz. Moreover, the memory and system performance of our proposal significantly outperforms the previous designs as shown in result section.
UR - http://www.scopus.com/inward/record.url?scp=44449135574&partnerID=8YFLogxK
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U2 - 10.1109/ISSPIT.2006.270822
DO - 10.1109/ISSPIT.2006.270822
M3 - Conference contribution
SN - 0780397541
SN - 9780780397545
T3 - Sixth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT
SP - 338
EP - 342
BT - Sixth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2006
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2006
Y2 - 27 August 2006 through 30 August 2006
ER -