Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches

Tsai Kan Chien; Lih Yih Chiou; Yi Sung Tsou; Shyh Shyuan Sheu; Pei Hua Wang; Ming Jinn Tsai; Chih I. Wu

doi:10.1109/ISLPED.2017.8009153

Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches

Tsai Kan Chien, Lih Yih Chiou, Yi Sung Tsou, Shyh Shyuan Sheu, Pei Hua Wang, Ming Jinn Tsai, Chih I. Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Nonvolatile static random-access memory (NV-SRAM) is a crucial component type for normally-off computing systems. This work proposes a novel 10T2R resistive random-access memory (ReRAM)-based NV-SRAM controller that is aware of redundant bit writes and considers the conditions of redundant bit writes. When data stored in SRAM cells are the same as the data in ReRAM devices, backup can be skipped. Otherwise, backup is performed. As a result, redundant bit-write conditions indicate that energy can be saved when backing up data. Simulations show that as much as 93% of typical energy requirements can be saved when the high resistive state is larger than 10 MΩ. As long as the probability of redundant bit writes is larger than 25%, backup energy saving can be achieved. The ReRAM chip is manufactured with 90 nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. This design can be applied to L2 and L3 caches.

Original language	English
Title of host publication	ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509060238
DOIs	https://doi.org/10.1109/ISLPED.2017.8009153
Publication status	Published - 2017 Aug 11
Event	22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan Duration: 2017 Jul 24 → 2017 Jul 26

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
Country/Territory	Taiwan
City	Taipei
Period	17-07-24 → 17-07-26

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/ISLPED.2017.8009153

Cite this

Chien, T. K., Chiou, L. Y., Tsou, Y. S., Sheu, S. S., Wang, P. H., Tsai, M. J., & Wu, C. I. (2017). Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches. In ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design [8009153] (Proceedings of the International Symposium on Low Power Electronics and Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISLPED.2017.8009153

Chien, Tsai Kan ; Chiou, Lih Yih ; Tsou, Yi Sung ; Sheu, Shyh Shyuan ; Wang, Pei Hua ; Tsai, Ming Jinn ; Wu, Chih I. / Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches. ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings of the International Symposium on Low Power Electronics and Design).

@inproceedings{f05d104eb3a44d3b874b872f2376fdf3,

title = "Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches",

abstract = "Nonvolatile static random-access memory (NV-SRAM) is a crucial component type for normally-off computing systems. This work proposes a novel 10T2R resistive random-access memory (ReRAM)-based NV-SRAM controller that is aware of redundant bit writes and considers the conditions of redundant bit writes. When data stored in SRAM cells are the same as the data in ReRAM devices, backup can be skipped. Otherwise, backup is performed. As a result, redundant bit-write conditions indicate that energy can be saved when backing up data. Simulations show that as much as 93% of typical energy requirements can be saved when the high resistive state is larger than 10 MΩ. As long as the probability of redundant bit writes is larger than 25%, backup energy saving can be achieved. The ReRAM chip is manufactured with 90 nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. This design can be applied to L2 and L3 caches.",

author = "Chien, {Tsai Kan} and Chiou, {Lih Yih} and Tsou, {Yi Sung} and Sheu, {Shyh Shyuan} and Wang, {Pei Hua} and Tsai, {Ming Jinn} and Wu, {Chih I.}",

note = "Funding Information: The authors thank the Ministry of Science and Technology, Taiwan for the research grant that supported this work (MOST 104-2220-E-006-015). Publisher Copyright: {\textcopyright} 2017 IEEE.; 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 ; Conference date: 24-07-2017 Through 26-07-2017",

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doi = "10.1109/ISLPED.2017.8009153",

language = "English",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

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Chien, TK, Chiou, LY, Tsou, YS, Sheu, SS, Wang, PH, Tsai, MJ & Wu, CI 2017, Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches. in ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design., 8009153, Proceedings of the International Symposium on Low Power Electronics and Design, Institute of Electrical and Electronics Engineers Inc., 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, 17-07-24. https://doi.org/10.1109/ISLPED.2017.8009153

Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches. / Chien, Tsai Kan; Chiou, Lih Yih; Tsou, Yi Sung; Sheu, Shyh Shyuan; Wang, Pei Hua; Tsai, Ming Jinn; Wu, Chih I.

ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2017. 8009153 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Chien, Tsai Kan

AU - Chiou, Lih Yih

AU - Tsou, Yi Sung

AU - Sheu, Shyh Shyuan

AU - Wang, Pei Hua

AU - Tsai, Ming Jinn

AU - Wu, Chih I.

PY - 2017/8/11

Y1 - 2017/8/11

N2 - Nonvolatile static random-access memory (NV-SRAM) is a crucial component type for normally-off computing systems. This work proposes a novel 10T2R resistive random-access memory (ReRAM)-based NV-SRAM controller that is aware of redundant bit writes and considers the conditions of redundant bit writes. When data stored in SRAM cells are the same as the data in ReRAM devices, backup can be skipped. Otherwise, backup is performed. As a result, redundant bit-write conditions indicate that energy can be saved when backing up data. Simulations show that as much as 93% of typical energy requirements can be saved when the high resistive state is larger than 10 MΩ. As long as the probability of redundant bit writes is larger than 25%, backup energy saving can be achieved. The ReRAM chip is manufactured with 90 nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. This design can be applied to L2 and L3 caches.

AB - Nonvolatile static random-access memory (NV-SRAM) is a crucial component type for normally-off computing systems. This work proposes a novel 10T2R resistive random-access memory (ReRAM)-based NV-SRAM controller that is aware of redundant bit writes and considers the conditions of redundant bit writes. When data stored in SRAM cells are the same as the data in ReRAM devices, backup can be skipped. Otherwise, backup is performed. As a result, redundant bit-write conditions indicate that energy can be saved when backing up data. Simulations show that as much as 93% of typical energy requirements can be saved when the high resistive state is larger than 10 MΩ. As long as the probability of redundant bit writes is larger than 25%, backup energy saving can be achieved. The ReRAM chip is manufactured with 90 nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. This design can be applied to L2 and L3 caches.

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PB - Institute of Electrical and Electronics Engineers Inc.

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Chien TK, Chiou LY, Tsou YS, Sheu SS, Wang PH, Tsai MJ et al. Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches. In ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc. 2017. 8009153. (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1109/ISLPED.2017.8009153

Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches

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