TY - GEN
T1 - X-on-interposer ecosystem to migrate IoT1.0 to value-added IoT2.0
AU - Fu, Chung Min
AU - Wang, Yun Che
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/21
Y1 - 2020/10/21
N2 - IoT applications normally involve heterogeneous integration of MCU, RF, sensor chips and discrete components, with the diversity but smaller quantity. PCB prototype is the first practical and cheap proof-of-concept (from 0 to 1) assembly using available package-ICs, components for initial functions test, software development and market trials, although with lower entry-barrier without much differentiation. SiP (system-in-package) is the next rationale revision option (from 1 to 2) for not only decent structural scaling, but also for system-level PPA (performance, power, formfactor and total cost) co-optimization, especially for the value-added sensor fusion, edge IoT2.0 applications or so called AIoT transformation.Such attempt of PCB migration to SiP options is not trivial to-be LEGO-like flows or simple ROI justification, if without deeper domain knowledges and chiplet design flow insights. Traditional SOC mindsets may be not sufficient, due to lacking system-level PPA(performance, power, area) considerations and more, such as thermal, stress management, decent what-if analysis and meaningful design-technology co-optimization among various structural stacking options. Some heterogenous cases are discussed in this article about IP/chip/package strategy, and potentially are developed for decent application-driven interposer platform technology proposals.
AB - IoT applications normally involve heterogeneous integration of MCU, RF, sensor chips and discrete components, with the diversity but smaller quantity. PCB prototype is the first practical and cheap proof-of-concept (from 0 to 1) assembly using available package-ICs, components for initial functions test, software development and market trials, although with lower entry-barrier without much differentiation. SiP (system-in-package) is the next rationale revision option (from 1 to 2) for not only decent structural scaling, but also for system-level PPA (performance, power, formfactor and total cost) co-optimization, especially for the value-added sensor fusion, edge IoT2.0 applications or so called AIoT transformation.Such attempt of PCB migration to SiP options is not trivial to-be LEGO-like flows or simple ROI justification, if without deeper domain knowledges and chiplet design flow insights. Traditional SOC mindsets may be not sufficient, due to lacking system-level PPA(performance, power, area) considerations and more, such as thermal, stress management, decent what-if analysis and meaningful design-technology co-optimization among various structural stacking options. Some heterogenous cases are discussed in this article about IP/chip/package strategy, and potentially are developed for decent application-driven interposer platform technology proposals.
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U2 - 10.1109/IMPACT50485.2020.9268589
DO - 10.1109/IMPACT50485.2020.9268589
M3 - Conference contribution
AN - SCOPUS:85098126932
T3 - Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT
SP - 121
EP - 124
BT - International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2020 and 22nd International Conference on Electronics Materials and Packaging, EMAP 2020 - Proceedings
PB - IEEE Computer Society
T2 - 15th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2020 and 22nd International Conference on Electronics Materials and Packaging, EMAP 2020
Y2 - 21 October 2020 through 23 October 2020
ER -