Yield enhancement by bad-die recycling and stacking with though-silicon vias

Yung Fa Chou, Ding Ming Kwai, Cheng Wen Wu

Research output: Contribution to journalArticle

18 Citations (Scopus)

Abstract

3-D integration provides a means to overcome the difficulties in design and manufacturing of system-on-chip (SOC) and memory products. Introducing a short vertical interconnect, called through-silicon via (TSV), makes it feasible to repair and recycle bad dies by stacking. We propose a method to accomplish this using a dual-TSV hardwired switch (DTHS) in which the via-hole location is programmable. With the DTHS, we activate a spare and establish inter-die routing. The spare is nothing but a good part in another bad die. To be 3-D reparable, the design is partitioned into disjoint parts. The effort for the modification is minor in view of that a typical SOC is readily composed of modules with predefined functions and supply voltages. The DTHS is used: 1) to shut off power connections of both failed and unused parts; 2) to disconnect their signal paths; and 3) to redirect them to the selected good parts in the stacked dies. Despite the speed is degraded due to the extra load incurred by the DTHS, our simulation shows that the increase in delay time can be limited below 100 ps with an over-designed buffer which occupies 0.8% of the area of a 30 μm TSV, using a 65-nm CMOS process. The performance degradation turns out to be a necessary evil, since the increased height of the die stack leads to a thermal conductivity poorer than its 2-D counterpart. The 3-D patch die helps to shorten time-to-market and turn the irreparable dies profitable.

Original languageEnglish
Article number5497215
Pages (from-to)1346-1356
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number8
DOIs
Publication statusPublished - 2011 Aug 1

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Recycling
Silicon
Switches
Thermal conductivity
Time delay
Repair
Data storage equipment
Degradation
Electric potential

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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Yield enhancement by bad-die recycling and stacking with though-silicon vias. / Chou, Yung Fa; Kwai, Ding Ming; Wu, Cheng Wen.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 8, 5497215, 01.08.2011, p. 1346-1356.

Research output: Contribution to journalArticle

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