以共濺鍍製備氧化鋁鋯介電層及鈦摻雜氧化銦鎵鋅通道層之薄膜電晶體

  • 林 呈修

Student thesis: Master's Thesis

Abstract

Date of Award2018 Aug 28
Original languageChinese
SupervisorShui-Jinn Wang (Supervisor)

Cite this

以共濺鍍製備氧化鋁鋯介電層及鈦摻雜氧化銦鎵鋅通道層之薄膜電晶體
呈修, 林. (Author). 2018 Aug 28

Student thesis: Master's Thesis