Abstract
Implementing circuit systems on the active matrix liquid crystal display (AMLCD) using low-temperature poly-silicon thin-film transistors (LTPS TFTs) has become a dominant trend in recent years. However, the variations of TFT electrical characteristics caused by the errors of fabrication processes might influence the stability of driver circuits. This defect might deteriorate the video quality of the display. The work proposes three driver circuits for flat panel display which are immune to the characteristic variations of LTPS TFTs. The feasibility of the proposed circuits will be verified through simulation and analysis.In this work, the electrical characteristics of the LTPS TFTs are measured for SPICE modeling to verify the effectiveness and reliability of the proposed circuits. The first proposed circuit is the source follower type analog buffer as announced by our laboratory. The simulation results show that the offset voltages are distributed within 0.12 V, and within 0.16 V in the worst case of Monte Carlo analysis, where the threshold voltage variation of LTPS TFT is set to 0.33 V. Additionally , the non-ideal factors generating error output of this circuit during operation are analyzed, and four main factors are concluded. Finally, the output error can be reduced by properly modulating the size of the coupling capacitor and the size of the specific transistor. The second proposed circuit is a source follower type analog buffer using a new self-compensating method. In this circuit, the active load is applied to the gate of the driving TFT for memorizing compensated voltage, and to the source of the driving TFT for eliminating the sub-threshold current. From the simulation, the gate voltages remain steady during the whole output period. The offset voltages are distributed within 0.16 V, and within 0.25 V in the worst case of Monte Carlo analysis. The third proposed circuit is a common electrode driving circuit design for a low-power panel system. The simple circuit structure has the advantages of maintaining low power consumption during the operating period and saving layout area. The simulation results show that no steady current is generated in this circuit during operation. Therefore, the circuit is able to be applied to low-power panel design. The performance of this circuit is investigated by simulating the driving capability on a 3•3 pixel array. The line inversion scheme performs an offset error below 0.06 V with capacitance loading varied from 20 pF to 200 pF, and the dot inversion scheme can perform an offset error below 0.08 V after optimization of circuit parameters.
| Date of Award | 2011 |
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| Original language | Chinese (Traditional) |