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卷積神經網路之硬體加速器設計
Translated title of the thesis
:
Hardware Accelerator Design for Convolutional Neural Networks
鄭 傑升
Student thesis
:
Master's Thesis
Date of Award
2019
Original language
Chinese
Supervisor
Wen-Long Chin
(Supervisor)
Cite this
Standard
卷積神經網路之硬體加速器設計
傑升, 鄭. (Author).
2019
Student thesis
:
Master's Thesis