Abstract
In recent years, using hydrogenated amorphous thin-film transistors (a-Si:H TFTs) to design driver circuits for active-matrix liquid crystal displays (AMLCDs) has attracted a large amount of attention because of the reduction in cost of fabrication and the increase in reliability. However, the severe threshold voltage (VTH) shift of a-Si:H TFTs which is caused by bias stress in addition to charge trapping and defect-state creation under long-term operation leads to the instability of driver circuits and subsequently affects the image quality of AMLCDs.This thesis proposes three gate driver circuits for which both the feasibility is verified through the Hspice simulator and the stability is proven by experimental results. The first gate driver circuit, composed of twelve a-Si:H TFTs, a capacitor and six clock signals, uses two opposite-phase and low-frequency clock signals to stabilize the row lines against floating and improve the power consumption. Furthermore, the reverse-bias scheme is applied to the gate-to-source voltage (VGS) of the pull-down TFTs to improve the VTH shift. According to the experimental results, the VTH variation is improved by 20.35% compared to that of TFTs under DC bias, and the power consumption is reduced by 47.02% relative to the conventional gate driver circuit. Additionally, this circuit can be operated over 240 hours at 100◦C, and the rising time (TRISE) and falling time (TFALL) of the output waveform are 7.8 μs and 5 μs, respectively. The second gate driver circuit, consisting of ten TFTs, one capacitor and six clock signals, continues with the concepts of the first gate driver circuit. Also, the number of components is lessened to further decrease the power consumption and reduce the layout area by approximately 17% compared to the first gate driver circuit. Based on the simulation results, the TRISE and TFALL are 5.5 μs and 3.8 μs, respectively. The third gate driver circuit is composed of nine TFTs, two capacitors and three clock signals. The new circuit reduces the number of clock signals and utilizes the AC-driving method to suppress the VTH shift of TFTs and prevent the row lines from floating. Moreover, modulating the gate bias of the pull-down TFTs can reduce power dissipation and further ameliorate the VTH shift to ensure the stability of the proposed circuit under long-term operation. Experimental results indicate that this circuit can operate stably over 240 hours at 60◦C. The TRISE and TFALL of the output waveform are 6.4 μs and 5.2 μs, respectively.
| Date of Award | 2012 |
|---|---|
| Original language | Chinese (Traditional) |
| Supervisor | Chih-Lung Lin (Supervisor) |