A 10-bit 120-MS/s SAR ADC with Compact Architecture and Noise Suppression Technique

  • 郭 哲勳

Student thesis: Master's Thesis


This thesis proposes three circuit design techniques for successive-approximation (SAR) analog-to-digital converters (ADCs) A single-channel 10-bit 180-MS/s asynchronous SAR ADC in 90-nm CMOS process was realized based on the proposed techniques First the compact combinational timing control technique is proposed to simplify the digital control circuitry and to reduce the dynamic switching power consumption The leakage problem from floating nodes is also removed to lower leakage power consumption and it makes the circuit more robust Second the enhanced asynchronous timing scheme is proposed to minimize the digital loop delay by taking both the output condition of the comparator and the DAC settling issue into consideration so that it can promote the operating speed of the SAR ADC Third the noise suppression technique is proposed to reduce the input-referred noise of the comparator without increasing the power consumption The proof-of-concept prototype was fabricated in TSMC 90-nm CMOS process The core area is 178 4 ?m × 78 25 ?m From measurement results at 0 9 V supply voltage and 120-MS/s sampling rate the total power consumption is 0 81 mW and ENOB is 9 26 bits It achieves a FoM of 11 fJ/conversion-step The measured DNL and INL are +0 3/-0 69 LSB and +0 59/-0 55 LSB respectively
Date of Award2014 Aug 22
Original languageEnglish
SupervisorSoon-Jyh Chang (Supervisor)

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