A 10-bit 300-MS/s Successive-Approximation Analog-to-Digital Converter with a Pre-amplifier-only Comparator

Abstract

A single-channel 10-bit 300-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) in 40-nm CMOS process is presented in this thesis We propose a hybrid architecture with one common DAC to implement a high-speed SAR ADC The operation speed is enhanced by adopting the loop-unrolled technique in the coarse conversions and timing control scheme with pre-amplifier-only comparator technique in the fine conversions Considering the mismatch between coarse and fine conversions we adopt the non-binary search scheme with redundancy to maintain the overall performance Moreover switchback capacitor switching method is also used which increases the speed of the comparison With the above-mentioned techniques it leads to a high-speed SAR ADC The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology The core area occupies 0 0289 mm2 At a supply voltage of 1 1-V and sampling rate of 300-MS/s the power consumption of the SAR ADC is 4 67 mW and the peak ENOB is 9 36 bits It achieves a figure of merit (FoM) of 23 6 fJ/conversion-step

Date of Award	2019
Original language	English
Supervisor	Soon-Jyh Chang (Supervisor)