A 10-bit 600-MS/s 2x-Interleaved Timing-Skew Insensitive Successive-Approximation Analog-to-Digital Converter

Abstract

This thesis presents a 10-bit 600-MS/s 2-way interleaved successive-approximation register (SAR) analog-to-digital converter (ADC) which is insensitive to the timing-skew The sub-range and multi-comparator architecture are adopted to implement the high speed sub-channel and the errors induced from this configuration are tolerated by manipulating the redundancy algorithm Thanks to the high speed sub-channel the sampling rate of 600-MS/s is achieved with merely two channels and the effect of timing-skew is well mitigated with the modified Track-and-Hold Circuit Hence the costly timing-skew calibration engine is no longer required in this work The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology of which the core circuits cover an area of 0 0963mm2 As the prototype operates at a supply voltage of 1 1-V and sampling rate of 600-MS/s the measurement result shows the prototype achieves 56 98 dB SNDR with low input frequency and 46 6 dB SNDR with input frequency up to Nyquist-rate Accordingly the Figure of Merit (FoM) are 21 2 fJ/conversion-step and 68 5 fJ/conversion-step respectively The tone induced by timing-skew error is -75 03 dB with a Nyquist-rate input for which the timing-skew between sub-channels is estimated to be as low as 94 fs

Date of Award	2019
Original language	English
Supervisor	Soon-Jyh Chang (Supervisor)