A 12-bit 4-MS/s Dual-Mode SAR ADC with Self-Biased Switching and Residue Oversampling Techniques

Abstract

This thesis presents a high-resolution 12-bit 4-MS/s dual-mode successive-approximation register (SAR) analog-to-digital converter (ADC) This SAR ADC adopts proposed Self-Biased Switching and Residue Oversampling techniques With the proposed Self-Biased Switching the comparison reference of single-ended mode could be generated before conversion Besides this method aligns this comparison reference with Vref enlarged For Residue Oversampling by repeating the residue voltage conversion and combining Dynamic Element Matching roles of capacitors are rearranged to generate different residue voltages Residue voltages output codes are averaged to generate a high-precision digital code By this technique the capacitor mismatch is reduced and accuracy of the ADC is improved without calibration The proof-of-concept 12-bit SAR ADC was fabricated in a HLMC 28-nm CMOS technology of which the core circuits occupy an area of 0 0665mm2 As the prototype operates at a supply voltage of 0 9 -V and sampling rate of 4-MS/s the simulation results show that the prototype ADC achieves 72 19 dB and 66 17 dB SNDR with a Nyquist-rate input in differential and single-ended modes respectively

Date of Award	2020
Original language	English
Supervisor	Soon-Jyh Chang (Supervisor)