A 14-bit 800MS/s 4-way Time-Interleaved Pipelined ADC with Digital Background Calibration

  • 廖 凡緯

Student thesis: Master's Thesis


Pipelined ADCs are usually implemented for high-speed high-resolution applications However to achieve high resolution the error induced by the opamp must be eliminated including finite opamp gain error opamp offset and distortion error This thesis proposes a dual-residue split-ADC architecture and digital background calibration technique for opamp errors so that a low-cost low-power amplifier could be used This architecture and calibration technique have the benefits of low complexity and high convergence Moreover these techniques can be used in time-interleaved pipelined ADCs Compared with the traditional TI-ADC the additional cost for calibrating channel mismatches which includes gain error mismatch and offset mismatch is unnecessary Besides the timing mismatch could be overcome by a bootstrapped switch which is embedded in the global sampling techniques proposed in this thesis The proposed dual-residue split-ADC and calibration technique are implemented in a 14-bit 800MS/s four-way time-interleaved pipelined ADC fabricated in TSMC 40nm 1P9M CMOS process A multi-bit front-end stage and open-loop architecture are implemented in this work for power saving The post-simulation results show that the SNDR before calibration is 37 3 dB and improved after calibration to 66 8 dB at 370MHz input frequency and 800MS/s sampling rate The power consumption is 83 8mW from a 1V supply excluding output buffer The Figure of Merit (FOM) of this prototype ADC is 58 5 fJ/conversion step
Date of Award2016 Jul 28
Original languageEnglish
SupervisorTai-Haur Kuo (Supervisor)

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