A Dynamic Body Bias CMOS Rectifier for High Sensitivity RF Energy Harvester

Abstract

This thesis presents a novel architecture rectifier for 900 MHz RF energy harvester applications In order to achieve the goal of high sensitivity this structure adds the compensation voltage to the bulk side of the MOS transistor to reduce the leakage current at discharging phase and increase the forward current at charging phase In the power conversion efficiency (PCE) of the overall RF energy harvester the co-design antenna with the rectifier can reduce the parasitic from the additional impedance matching circuit Chapter 1 introduce the development of energy harvester application and the design consideration of the RF energy harvester system The system architecture and parameter definition of the RF energy harvesters are discussed in chapter 2 Chapter 3 compared the advantages and disadvantages of the previous architecture of the CMOS rectifier The implementation of the proposed structure and the design condition are presented in chapter 4 Chapter 5 shows the testing setups and the measurement results There are two wireless measurement setup First a commercial 50 ? antenna impedance matching network Secondly a co-design antenna with rectifier At the commercial 50 ? antenna measurement the harvester system has 1 V output voltage and 0 2 MΩ load at an input power of -19 4 dBm The power conversion efficiency (PCE) is 43 6 % The co-design antenna wireless measurement achieves -18 dBm with 0 2 MΩ load Significantly improved compared to the previous work of the lab The PCE increased from 15% to 43 6 % under the same 1 MΩ load The chip area is 0 94 × 0 645 ?mm?^2 and the area of all PCB (Printed Circuit Board) while included the antenna is 60 × 40 mm2

Date of Award	2019
Original language	English
Supervisor	Kuang-Wei Cheng (Supervisor)