A First-order Low Distortion Sigma-Delta Modulator Using Split DWA Technique and SAR Quantizer

Abstract

With the evolution of the modern process the performance of analog components suffers from the severe short channel effects Therefore novel design techniques and architectures which are able to release the burden of analog design efforts is important This thesis presents a first-order low distortion sigma-delta modulator (SDM) using split data-weighted-averaging (DWA) algorithm and successive-approximation register (SAR) quantizer to achieve low power low area and wide bandwidth SDM In this work a comparator-based operational amplifier instead of the conventional one is utilized in the integrator to release the design complexity for operational amplifier in advanced process In the meanwhile a low distortion structure with small output swing can relax the design effort and improve the linearity of whole modulator On the top of that to reduce the power consumption a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation Moreover a proposed split DWA simplifies the digital control logic for higher resolution quantizer to save the silicon area The modulator core occupies an active area of 0 0275 mm2 in TSMC 90-nm 1P9M CMOS process The experimental results show that the proposed modulator achieves 59 90 dB SNDR with 0 58 mW power consumption under 1 0 V supply voltage an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency

Date of Award	2014 Aug 29
Original language	English
Supervisor	Soon-Jyh Chang (Supervisor)