A Low Area Overhead BIST Architecture Based on Response Feedback and Logic Reseeding

Abstract

The built-in self-test (BIST) scheme which adopts circular self-test path (CSTP) is an attractive technique for testing integrated circuits It can compact output response of the circuit under test (CUT) and generate a new pattern concurrently As a result it does not required an additional module for response analysis Moreover some papers use internal response from the CUT to generate deterministic patterns In this thesis a new BIST scheme is proposed which adopts a special test generator that can generate patterns and compact output response of the CUT And the proposed method utilizes very few internal nets of the CUT to generate all required data without any storage requirement In addition observation point insertion is employed to increase random testability of faults Experimental results show that the proposed approach can achieve 100% fault coverage by average 0 0837% and 0 0303% of internal nets that include inserted observation points and with average 2 27% and 1 79% gate area overhead on ISCAS and IWLS benchmark circuits respectively In addition our approach can reduce the hardware about response compaction significantly

Date of Award	2014 Aug 11
Original language	English
Supervisor	Kuen-Jong Lee (Supervisor)