A Low-Cost VLSI Architecture of Bilateral Filter for Image Denoising

  • 鄧 悅翎

Student thesis: Master's Thesis


Real-world images may be dominated by all kinds of noises due to many reasons In most case these noises will interfere with the usage of the images Thus the technology of noise reduction is very important in processing images In the field of image noise reduction there is a major concern in removing noises from the images and at the same time without damaging the characteristics of it Among the technologies of noise reduction bilateral filtering is the most well-known technique in the field of image processing The major advantage of using the bilateral filter is that it removes the noise from the images while retaining the details of the image’s edges It is the reason why the bilateral filter is widely used and became the base form of many other extension methods In real time application the computational complexity of the bilateral filter is very high So in recent years some studies have proposed a hardware implementation of bilateral filter in order to improve its speed Although these methods are able to improve the speed of processing however their hardware cost could be further improved In this thesis a low-cost and real-time VLSI architecture is proposed Data path optimization and resource sharing were applied to reduce the number of multipliers In addition a special purpose look-up table is proposed to reduce the required memory space As a result the cost of hardware is reduced The VLSI architecture is implemented by using Verilog hardware description language and synthesized by using Xilinx ISE 14 7 WebPACK version According to our experimental results the proposed design reduces the cost of hardware without compromising the image quality in comparison with the existing literature Besides that it is able to achieve real-time processing
Date of Award2016 Feb 4
Original languageEnglish
SupervisorPei-Yin Chen (Supervisor)

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